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New: Add TUI (#13) AXI-CROSSBAR #100: Commit 0271de4 pushed by dpretet
2h 16m 0s issue13
issue13
2h 16m 0s
New: Start RTL generator dev with Mistral Vibe CLI (#13) AXI-CROSSBAR #99: Commit 8b696a2 pushed by dpretet
2h 6m 15s issue13
issue13
2h 6m 15s
Continue rework the genericity of master/slave number (#12 & #13) AXI-CROSSBAR #98: Commit 323a515 pushed by dpretet
1h 10m 19s issue12
issue12
1h 10m 19s
Change: Add NUM_PRIORITY_LVL paramter AXI-CROSSBAR #97: Commit a544cd3 pushed by dpretet
54s issue12
issue12
54s
New: First attempt to rework arbitration per level (#12) AXI-CROSSBAR #96: Commit 39ab24f pushed by dpretet
1h 50m 50s issue12
issue12
1h 50m 50s
New: First attempt to rework arbitration per level (#12) AXI-CROSSBAR #95: Commit 778e0be pushed by dpretet
1h 51m 50s issue12
issue12
1h 51m 50s
Fix: aw misroute signal was used in w channel signals (#12) AXI-CROSSBAR #94: Commit b2f9900 pushed by dpretet
1h 49m 39s issue12
issue12
1h 49m 39s
Issue #12 - Support any number of slave / master agents AXI-CROSSBAR #93: Commit 078aff8 pushed by dpretet
1h 55m 55s issue12
issue12
1h 55m 55s
Change: Use AXI_SIGNALING=1 by default for AXI4 top level AXI-CROSSBAR #92: Commit 7d6d2a5 pushed by dpretet
1h 53m 17s issue12
issue12
1h 53m 17s
Change: Use packed parameters to let the switching logic top level ve… AXI-CROSSBAR #91: Commit 932ab57 pushed by dpretet
1m 4s issue12
issue12
1m 4s
Change: Use packed parameters to let the switching logic top level ve… AXI-CROSSBAR #90: Commit 009101a pushed by dpretet
1m 0s issue12
issue12
1m 0s
Change: Use AXI_SIGNALING=1 by default for AXI4 top level AXI-CROSSBAR #89: Commit 7d6d2a5 pushed by dpretet
2h 5m 21s main
main
2h 5m 21s
Change: rework a process to pass verilator compilation in simulation AXI-CROSSBAR #88: Commit 7d6ba25 pushed by dpretet
1h 59m 5s v1.1.1
v1.1.1
1h 59m 5s
Change: rework a process to pass verilator compilation in simulation AXI-CROSSBAR #87: Commit 7d6ba25 pushed by dpretet
1h 58m 39s main
main
1h 58m 39s
Add area estimation, but yosys scripts need to be fine-tuned. Not yet… AXI-CROSSBAR #86: Commit 3ebf3df pushed by dpretet
1h 55m 6s v1.1.0
v1.1.0
1h 55m 6s
Add area estimation, but yosys scripts need to be fine-tuned. Not yet… AXI-CROSSBAR #85: Commit 3ebf3df pushed by dpretet
1h 44m 50s main
main
1h 44m 50s
Merge main branch AXI-CROSSBAR #84: Commit 0e8580c pushed by dpretet
1h 48m 53s ordering
ordering
1h 48m 53s
Fix: #20 issue - misrouted write completion AXI-CROSSBAR #83: Commit 89668b4 pushed by dpretet
1h 46m 52s ordering
ordering
1h 46m 52s
Fix: AXI4 misrouted read completion if ALEN>0 was interleaved because AXI-CROSSBAR #82: Commit df225c8 pushed by dpretet
1h 40m 24s ordering
ordering
1h 40m 24s
Fix: read completion channel if OR=1 didn't responsed correctly if AXI-CROSSBAR #81: Commit 361a4a0 pushed by dpretet
1h 49m 58s ordering
ordering
1h 49m 58s
Change: rewrite ordering rules management chapter AXI-CROSSBAR #80: Commit 287a92f pushed by dpretet
1h 7m 48s ordering
ordering
1h 7m 48s
Change: Update documentation to add OoO support mentions AXI-CROSSBAR #79: Commit 640272d pushed by dpretet
1h 22m 26s ordering
ordering
1h 22m 26s
New: add a full support OoO to read channel of slave switch AXI-CROSSBAR #78: Commit 5a4e255 pushed by dpretet
1h 14m 23s ordering
ordering
1h 14m 23s
Change: Split CI synthesis in two AXI4 and AXI4-lite jobs AXI-CROSSBAR #77: Commit 2836a75 pushed by dpretet
1h 37m 19s ordering
ordering
1h 37m 19s
New: Split regression by running AXI4 and AXI4-lite separately AXI-CROSSBAR #76: Commit 755cd38 pushed by dpretet
1h 47m 56s ordering
ordering
1h 47m 56s