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New: add a full support OoO to read channel of slave switch
1 parent 2836a75 commit 5a4e255

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4 files changed

+252
-242
lines changed

4 files changed

+252
-242
lines changed

‎rtl/axicb_slv_ooo.sv‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -61,12 +61,8 @@ module axicb_slv_ooo
6161
// side to avoid comb loop
6262
input wire [SLV_NB -1:0] c_valid,
6363
input wire c_ready,
64-
input wire [SLV_NB -1:0] c_last,
6564
input wire [CCH_W*SLV_NB -1:0] c_ch,
66-
input wire c_end,
67-
// Last flag recreated when misrouted completion occurs
68-
// Avoid combinatorial loop
69-
input wire mr_last
65+
input wire c_end
7066
);
7167

7268
////////////////////////////////////////////////////////////////

‎rtl/axicb_slv_switch_rd.sv‎

Lines changed: 95 additions & 116 deletions
Original file line numberDiff line numberDiff line change
@@ -78,12 +78,21 @@ module axicb_slv_switch_rd
7878

7979

8080
logic [SLV_NB -1:0] slv_ar_targeted;
81+
logic ar_misrouting_c;
82+
logic ar_misrouting;
83+
logic [8 -1:0] a_len;
8184

8285
logic rch_en;
8386
logic rch_en_r;
8487
logic rfirst;
85-
logic [SLV_NB -1:0] rch_req;
88+
logic rch_mr;
89+
logic [AXI_ID_W -1:0] rch_id;
90+
logic [8 -1:0] rch_len;
8691
logic [SLV_NB -1:0] rch_grant;
92+
logic [8 -1:0] rlen;
93+
logic rch_running;
94+
logic rch_full;
95+
logic c_end;
8796

8897
logic [AXI_ADDR_W-1:0] slv0_start_addr = SLV0_START_ADDR[0+:AXI_ADDR_W];
8998
logic [AXI_ADDR_W-1:0] slv0_end_addr = SLV0_END_ADDR[0+:AXI_ADDR_W];
@@ -94,18 +103,6 @@ module axicb_slv_switch_rd
94103
logic [AXI_ADDR_W-1:0] slv3_start_addr = SLV3_START_ADDR[0+:AXI_ADDR_W];
95104
logic [AXI_ADDR_W-1:0] slv3_end_addr = SLV3_END_ADDR[0+:AXI_ADDR_W];
96105

97-
logic r_misrouting;
98-
99-
logic rch_mr_full;
100-
logic rch_mr_empty;
101-
102-
logic [AXI_ID_W+8-1:0] rch_mr_info;
103-
logic [AXI_ID_W -1:0] rch_mr_id;
104-
logic [8 -1:0] rch_mr_len;
105-
logic [8 -1:0] rlen;
106-
logic rch_running;
107-
108-
logic [SLV_NB -1:0] routes = MST_ROUTES;
109106

110107
///////////////////////////////////////////////////////////////////////////
111108
// Read Address Channel
@@ -156,22 +153,24 @@ module axicb_slv_switch_rd
156153
(slv_ar_targeted[1]) ? o_arready[1]:
157154
(slv_ar_targeted[2]) ? o_arready[2]:
158155
(slv_ar_targeted[3]) ? o_arready[3]:
159-
r_misrouting;
156+
ar_misrouting;
160157

161158
assign o_arch = i_arch;
162159

160+
assign ar_misrouting_c = slv_ar_targeted=='0;
161+
163162
// Create a fake ready handshake in case a master agent targets a
164163
// forbidden or undefined memory space
165164
always @ (posedge aclk or negedge aresetn) begin
166165
if (!aresetn) begin
167-
r_misrouting <= 1'b0;
166+
ar_misrouting <= 1'b0;
168167
end else if (srst) begin
169-
r_misrouting <= 1'b0;
168+
ar_misrouting <= 1'b0;
170169
end else begin
171-
if (r_misrouting) begin
172-
r_misrouting <= 1'b0;
173-
end else if (i_arvalid && |slv_ar_targeted==1'b0 && !rch_mr_full) begin
174-
r_misrouting <= 1'b1;
170+
if (ar_misrouting) begin
171+
ar_misrouting <= 1'b0;
172+
end else if (i_arvalid && ar_misrouting_c) begin
173+
ar_misrouting <= 1'b1;
175174
end
176175
end
177176
end
@@ -181,99 +180,68 @@ module axicb_slv_switch_rd
181180
///////////////////////////////////////////////////////////////////////////
182181

183182
generate
184-
// Gather ARLEN and ARID to pass them to the completion circuit returning
185-
// the DECERR completion in case of misrouting
186-
if (AXI_SIGNALING>0)
187-
begin: AXI_SUPPORT
188-
assign rch_mr_info = {i_arch[AXI_ADDR_W+AXI_ID_W+:8], i_arch[AXI_ADDR_W+:AXI_ID_W]};
189-
end else
190-
begin: AXI4_LITE_SUPPORT
191-
assign rch_mr_info = {8'h0, i_arch[AXI_ADDR_W+:AXI_ID_W]};
183+
if (AXI_SIGNALING) begin: AXI4_ALEN
184+
assign a_len = i_arch[AXI_ADDR_W+AXI_ID_W+:8];
185+
end else begin: AXI4LITE_ALEN0
186+
assign a_len = '0;
192187
end
193188
endgenerate
194189

195-
196-
// FIFO storing the misrouting completion to return
197-
axicb_scfifo
190+
// OoO ID Management
191+
axicb_slv_ooo
198192
#(
199-
.PASS_THRU (0),
200-
.ADDR_WIDTH (4),
201-
.DATA_WIDTH (AXI_ID_W+8)
193+
.RD_PATH (1),
194+
.AXI_ID_W (AXI_ID_W),
195+
.SLV_NB (SLV_NB),
196+
.MST_OSTDREQ_NUM (MST_OSTDREQ_NUM),
197+
.MST_ID_MASK (MST_ID_MASK),
198+
.CCH_W (RCH_W)
202199
)
203-
rch_mr_fifo
200+
bresp_ooo
204201
(
205-
.aclk (aclk),
206-
.aresetn (aresetn),
207-
.srst (srst),
208-
.flush (1'b0),
209-
.data_in (rch_mr_info),
210-
.push (r_misrouting),
211-
.full (rch_mr_full),
212-
.data_out ({rch_mr_len, rch_mr_id}),
213-
.pull (i_rvalid & i_rready & i_rlast & !rch_running),
214-
.empty (rch_mr_empty)
202+
.aclk (aclk),
203+
.aresetn (aresetn),
204+
.srst (srst),
205+
.a_valid (i_arvalid),
206+
.a_ready (i_arready),
207+
.a_full (rch_full),
208+
.a_id (i_arch[AXI_ADDR_W+:AXI_ID_W]),
209+
.a_len (a_len),
210+
.a_ix (slv_ar_targeted),
211+
.a_mr (ar_misrouting_c),
212+
.c_en (rch_en),
213+
.c_grant (rch_grant),
214+
.c_mr (rch_mr),
215+
.c_id (rch_id),
216+
.c_len (rch_len),
217+
.c_valid (o_rvalid),
218+
.c_ready (i_rready),
219+
.c_ch (o_rch),
220+
.c_end (c_end)
215221
);
216222

217223

218-
// rch_running prevents misrouted completion to be routed-back
219-
// the corresponding master.
220-
// rlen is the length of the misrouted packet
224+
assign c_end = i_rvalid & i_rready & i_rlast;
225+
226+
// Follow-up rcompletion len for mis-routed traffic
227+
// which need to be recreated
221228
always @ (posedge aclk or negedge aresetn) begin
222229
if (!aresetn) begin
223230
rlen <= 8'h0;
224-
rch_running <= 1'b0;
225231
end else if (srst) begin
226232
rlen <= 8'h0;
227-
rch_running <= 1'b0;
228233
end else begin
229234

230-
if (rch_running && i_rvalid && i_rready && i_rlast) begin
231-
rch_running <= 1'b0;
232-
end else if (rch_mr_empty && i_rvalid && !i_rlast) begin
233-
rch_running <= 1'b1;
234-
end
235-
236-
if (rch_mr_empty) begin
237-
rlen <= 8'h0;
238-
end else if (i_rvalid && i_rready && i_rlast && !rch_running) begin
235+
if (i_rvalid && i_rready && i_rlast) begin
239236
rlen <= 8'h0;
240237
end else begin
241-
if (i_rvalid && i_rready && !rch_running) begin
238+
if (i_rvalid && i_rready) begin
242239
rlen <= rlen + 1'b1;
243240
end
244241
end
245242
end
246243
end
247244

248-
axicb_round_robin
249-
#(
250-
.REQ_NB (SLV_NB),
251-
.REQ0_PRIORITY (0),
252-
.REQ1_PRIORITY (0),
253-
.REQ2_PRIORITY (0),
254-
.REQ3_PRIORITY (0)
255-
)
256-
rch_round_robin
257-
(
258-
.aclk (aclk),
259-
.aresetn (aresetn),
260-
.srst (srst),
261-
.en (rch_en),
262-
.req (rch_req),
263-
.grant (rch_grant)
264-
);
265-
266-
always @ (posedge aclk or negedge aresetn) begin
267-
if (!aresetn) begin
268-
rch_en_r <= '0;
269-
end else if (srst) begin
270-
rch_en_r <= '0;
271-
end else begin
272-
if (rch_grant=='0) rch_en_r <= 1'b1;
273-
else rch_en_r <= 1'b0;
274-
end
275-
end
276-
277245
// Indicates the first read completion dataphase
278246
always @ (posedge aclk or negedge aresetn) begin
279247
if (!aresetn) begin
@@ -288,35 +256,46 @@ module axicb_slv_switch_rd
288256
end
289257
end
290258

259+
260+
always @ (posedge aclk or negedge aresetn) begin
261+
if (!aresetn) begin
262+
rch_en_r <= '0;
263+
end else if (srst) begin
264+
rch_en_r <= '0;
265+
end else begin
266+
if (rch_grant=='0) rch_en_r <= 1'b1;
267+
else rch_en_r <= 1'b0;
268+
end
269+
end
270+
271+
291272
assign rch_en = rfirst | rch_en_r;
292273

293-
assign rch_req = o_rvalid;
294-
295-
assign i_rvalid = (!rch_mr_empty && !rch_running) ? 1'b1 :
296-
(rch_grant[0]) ? o_rvalid[0] :
297-
(rch_grant[1]) ? o_rvalid[1] :
298-
(rch_grant[2]) ? o_rvalid[2] :
299-
(rch_grant[3]) ? o_rvalid[3] :
300-
1'b0;
301-
302-
assign i_rlast = (!rch_mr_empty && !rch_running) ? (rlen==rch_mr_len) & i_rvalid & i_rready :
303-
(rch_grant[0]) ? o_rlast[0] :
304-
(rch_grant[1]) ? o_rlast[1] :
305-
(rch_grant[2]) ? o_rlast[2] :
306-
(rch_grant[3]) ? o_rlast[3] :
307-
1'b0;
308-
309-
assign o_rready[0] = rch_grant[0] & i_rready & (rch_mr_empty | rch_running);
310-
assign o_rready[1] = rch_grant[1] & i_rready & (rch_mr_empty | rch_running);
311-
assign o_rready[2] = rch_grant[2] & i_rready & (rch_mr_empty | rch_running);
312-
assign o_rready[3] = rch_grant[3] & i_rready & (rch_mr_empty | rch_running);
313-
314-
assign i_rch = (!rch_mr_empty && !rch_running) ? {{RCH_W-AXI_ID_W-2{1'b0}}, 2'h3, rch_mr_id} :
315-
(rch_grant[0]) ? o_rch[0*RCH_W+:RCH_W] :
316-
(rch_grant[1]) ? o_rch[1*RCH_W+:RCH_W] :
317-
(rch_grant[2]) ? o_rch[2*RCH_W+:RCH_W] :
318-
(rch_grant[3]) ? o_rch[3*RCH_W+:RCH_W] :
319-
{RCH_W{1'b0}};
274+
assign i_rvalid = (rch_mr) ? 1'b1 :
275+
(rch_grant[0]) ? o_rvalid[0] :
276+
(rch_grant[1]) ? o_rvalid[1] :
277+
(rch_grant[2]) ? o_rvalid[2] :
278+
(rch_grant[3]) ? o_rvalid[3] :
279+
1'b0;
280+
281+
assign i_rlast = (rch_mr) ? (rlen==rch_len) & i_rvalid & i_rready :
282+
(rch_grant[0]) ? o_rlast[0] :
283+
(rch_grant[1]) ? o_rlast[1] :
284+
(rch_grant[2]) ? o_rlast[2] :
285+
(rch_grant[3]) ? o_rlast[3] :
286+
1'b0;
287+
288+
assign o_rready[0] = rch_grant[0] & i_rready & !rch_mr;
289+
assign o_rready[1] = rch_grant[1] & i_rready & !rch_mr;
290+
assign o_rready[2] = rch_grant[2] & i_rready & !rch_mr;
291+
assign o_rready[3] = rch_grant[3] & i_rready & !rch_mr;
292+
293+
assign i_rch = (!rch_mr) ? {'0, 2'h3, rch_id} :
294+
(rch_grant[0]) ? o_rch[0*RCH_W+:RCH_W] :
295+
(rch_grant[1]) ? o_rch[1*RCH_W+:RCH_W] :
296+
(rch_grant[2]) ? o_rch[2*RCH_W+:RCH_W] :
297+
(rch_grant[3]) ? o_rch[3*RCH_W+:RCH_W] :
298+
{RCH_W{1'b0}};
320299

321300
endmodule
322301

‎rtl/axicb_slv_switch_wr.sv‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -262,10 +262,8 @@ module axicb_slv_switch_wr
262262
.c_len (/*unused*/),
263263
.c_valid (o_bvalid),
264264
.c_ready (i_bready),
265-
.c_last ('1),
266265
.c_ch (o_bch),
267-
.c_end (c_end),
268-
.mr_last (1'b1)
266+
.c_end (c_end)
269267
);
270268

271269
assign c_end = i_bvalid & i_bready;

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