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Change: Use packed parameters to let the switching logic top level very generic (#12)
1 parent 7d6d2a5 commit 932ab57

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2 files changed

+35
-56
lines changed

2 files changed

+35
-56
lines changed

‎rtl/axicb_crossbar_top.sv‎

Lines changed: 9 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,6 +1137,11 @@ module axicb_crossbar_top
11371137
// AXI switching logic
11381138
///////////////////////////////////////////////////////////////////////////
11391139

1140+
localparam [MST_NB*AXI_ID_W-1:0] MST_ID_MASK = {MST3_ID_MASK, MST2_ID_MASK, MST1_ID_MASK, MST0_ID_MASK};
1141+
localparam [MST_NB*2-1:0] MST_PRIORITY = {MST3_PRIORITY, MST2_PRIORITY, MST1_PRIORITY, MST0_PRIORITY};
1142+
localparam [SLV_NB*AXI_ADDR_W-1:0] SLV_START_ADDR = {SLV3_START_ADDR, SLV2_START_ADDR, SLV1_START_ADDR, SLV0_START_ADDR};
1143+
localparam [SLV_NB*AXI_ADDR_W-1:0] SLV_END_ADDR = {SLV3_END_ADDR, SLV2_END_ADDR, SLV1_END_ADDR, SLV0_END_ADDR};
1144+
11401145
axicb_switch_top
11411146
#(
11421147
.AXI_ADDR_W (AXI_ADDR_W),
@@ -1148,24 +1153,12 @@ module axicb_crossbar_top
11481153
.MST_PIPELINE (MST_PIPELINE),
11491154
.SLV_PIPELINE (SLV_PIPELINE),
11501155
.TIMEOUT_ENABLE (TIMEOUT_ENABLE),
1151-
.MST0_ID_MASK (MST0_ID_MASK),
1152-
.MST1_ID_MASK (MST1_ID_MASK),
1153-
.MST2_ID_MASK (MST2_ID_MASK),
1154-
.MST3_ID_MASK (MST3_ID_MASK),
1156+
.MST_ID_MASK (MST_ID_MASK),
1157+
.MST_PRIORITY (MST_PRIORITY),
11551158
.MST_OSTDREQ_NUM (MST_OSTDREQ_NUM),
11561159
.MST_ROUTES (MST_ROUTES),
1157-
.MST0_PRIORITY (MST0_PRIORITY),
1158-
.MST1_PRIORITY (MST1_PRIORITY),
1159-
.MST2_PRIORITY (MST2_PRIORITY),
1160-
.MST3_PRIORITY (MST3_PRIORITY),
1161-
.SLV0_START_ADDR (SLV0_START_ADDR),
1162-
.SLV0_END_ADDR (SLV0_END_ADDR),
1163-
.SLV1_START_ADDR (SLV1_START_ADDR),
1164-
.SLV1_END_ADDR (SLV1_END_ADDR),
1165-
.SLV2_START_ADDR (SLV2_START_ADDR),
1166-
.SLV2_END_ADDR (SLV2_END_ADDR),
1167-
.SLV3_START_ADDR (SLV3_START_ADDR),
1168-
.SLV3_END_ADDR (SLV3_END_ADDR),
1160+
.SLV_START_ADDR (SLV_START_ADDR),
1161+
.SLV_END_ADDR (SLV_END_ADDR),
11691162
.AWCH_W (AWCH_W),
11701163
.WCH_W (WCH_W),
11711164
.BCH_W (BCH_W),

‎rtl/axicb_switch_top.sv‎

Lines changed: 26 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -33,30 +33,18 @@ module axicb_switch_top
3333
// Routes to the slaves allowed per master
3434
parameter [MST_NB*SLV_NB -1:0] MST_ROUTES = 16'hFFFF,
3535

36-
// Masters ID mask
37-
parameter [AXI_ID_W-1:0] MST0_ID_MASK = 'h00,
38-
parameter [AXI_ID_W-1:0] MST1_ID_MASK = 'h10,
39-
parameter [AXI_ID_W-1:0] MST2_ID_MASK = 'h20,
40-
parameter [AXI_ID_W-1:0] MST3_ID_MASK = 'h30,
41-
42-
// Masters priorities
43-
parameter MST0_PRIORITY = 0,
44-
parameter MST1_PRIORITY = 0,
45-
parameter MST2_PRIORITY = 0,
46-
parameter MST3_PRIORITY = 0,
47-
48-
// Masters Outstanding Requests Number
36+
// Masters ID mask (packed)
37+
parameter [MST_NB*AXI_ID_W-1:0] MST_ID_MASK = 'h30_20_10_00,
38+
39+
// Masters priorities (packed)
40+
parameter [MST_NB*2-1:0] MST_PRIORITY = 'h0_0_0_0,
41+
42+
// Masters Outstanding Requests Number (packed)
4943
parameter [MST_NB*8-1:0] MST_OSTDREQ_NUM = 'h4_4_4_4,
5044

51-
// Slaves memory mapping
52-
parameter SLV0_START_ADDR = 0,
53-
parameter SLV0_END_ADDR = 4095,
54-
parameter SLV1_START_ADDR = 4096,
55-
parameter SLV1_END_ADDR = 8191,
56-
parameter SLV2_START_ADDR = 8192,
57-
parameter SLV2_END_ADDR = 12287,
58-
parameter SLV3_START_ADDR = 12288,
59-
parameter SLV3_END_ADDR = 16383,
45+
// Slaves memory mapping (packed)
46+
parameter [SLV_NB*AXI_ADDR_W-1:0] SLV_START_ADDR = 'h0000_2000_1000_0000,
47+
parameter [SLV_NB*AXI_ADDR_W-1:0] SLV_END_ADDR = 'h3FFF_2FFF_1FFF_0FFF,
6048

6149
// Channels' width (concatenated)
6250
parameter AWCH_W = 8,
@@ -108,8 +96,6 @@ module axicb_switch_top
10896
);
10997

11098
genvar i, j;
111-
112-
parameter [4*AXI_ID_W-1:0] MST_ID_MASK = {MST3_ID_MASK,MST2_ID_MASK,MST1_ID_MASK,MST0_ID_MASK};
11399

114100
// master <> slave logic routing
115101
logic [MST_NB*SLV_NB -1:0] slv_awvalid;
@@ -269,14 +255,14 @@ module axicb_switch_top
269255
.MST_OSTDREQ_NUM (MST_OSTDREQ_NUM[i*8+:8]),
270256
.MST_ID_MASK (MST_ID_MASK[i*AXI_ID_W+:AXI_ID_W]),
271257
.TIMEOUT_ENABLE (TIMEOUT_ENABLE),
272-
.SLV0_START_ADDR (SLV0_START_ADDR),
273-
.SLV0_END_ADDR (SLV0_END_ADDR),
274-
.SLV1_START_ADDR (SLV1_START_ADDR),
275-
.SLV1_END_ADDR (SLV1_END_ADDR),
276-
.SLV2_START_ADDR (SLV2_START_ADDR),
277-
.SLV2_END_ADDR (SLV2_END_ADDR),
278-
.SLV3_START_ADDR (SLV3_START_ADDR),
279-
.SLV3_END_ADDR (SLV3_END_ADDR),
258+
.SLV0_START_ADDR (SLV_START_ADDR[i*AXI_ADDR_W+:AXI_ADDR_W]),
259+
.SLV0_END_ADDR (SLV_END_ADDR[i*AXI_ADDR_W+:AXI_ADDR_W]),
260+
.SLV1_START_ADDR (SLV_START_ADDR[(i+1)*AXI_ADDR_W+:AXI_ADDR_W]),
261+
.SLV1_END_ADDR (SLV_END_ADDR[(i+1)*AXI_ADDR_W+:AXI_ADDR_W]),
262+
.SLV2_START_ADDR (SLV_START_ADDR[(i+2)*AXI_ADDR_W+:AXI_ADDR_W]),
263+
.SLV2_END_ADDR (SLV_END_ADDR[(i+2)*AXI_ADDR_W+:AXI_ADDR_W]),
264+
.SLV3_START_ADDR (SLV_START_ADDR[(i+3)*AXI_ADDR_W+:AXI_ADDR_W]),
265+
.SLV3_END_ADDR (SLV_END_ADDR[(i+3)*AXI_ADDR_W+:AXI_ADDR_W]),
280266
.AWCH_W (AWCH_W),
281267
.WCH_W (WCH_W),
282268
.BCH_W (BCH_W),
@@ -407,14 +393,14 @@ module axicb_switch_top
407393
.AXI_DATA_W (AXI_DATA_W),
408394
.MST_NB (MST_NB),
409395
.TIMEOUT_ENABLE (TIMEOUT_ENABLE),
410-
.MST0_ID_MASK (MST0_ID_MASK),
411-
.MST1_ID_MASK (MST1_ID_MASK),
412-
.MST2_ID_MASK (MST2_ID_MASK),
413-
.MST3_ID_MASK (MST3_ID_MASK),
414-
.MST0_PRIORITY (MST0_PRIORITY),
415-
.MST1_PRIORITY (MST1_PRIORITY),
416-
.MST2_PRIORITY (MST2_PRIORITY),
417-
.MST3_PRIORITY (MST3_PRIORITY),
396+
.MST0_ID_MASK (MST_ID_MASK[0*AXI_ID_W+:AXI_ID_W]),
397+
.MST1_ID_MASK (MST_ID_MASK[1*AXI_ID_W+:AXI_ID_W]),
398+
.MST2_ID_MASK (MST_ID_MASK[2*AXI_ID_W+:AXI_ID_W]),
399+
.MST3_ID_MASK (MST_ID_MASK[3*AXI_ID_W+:AXI_ID_W]),
400+
.MST0_PRIORITY (MST_PRIORITY[0*2+:2]),
401+
.MST1_PRIORITY (MST_PRIORITY[1*2+:2]),
402+
.MST2_PRIORITY (MST_PRIORITY[2*2+:2]),
403+
.MST3_PRIORITY (MST_PRIORITY[3*2+:2]),
418404
.AWCH_W (AWCH_W),
419405
.WCH_W (WCH_W),
420406
.BCH_W (BCH_W),

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