Skip to content

Commit 078aff8

Browse files
dpretetdpretet
committed
Issue #12 - Support any number of slave / master agents
Rework the switching logic to use a set of packed parameters insteads of individuals. Four paramters have been reworked: - MST_ROUTES - MST_PRIORITY - MST_ID_MASK - SLV_START_ADDR / SLV_END_ADDR Remains the round robin top level core to upgrade to take in account the genericity required, today still only works with 4/4 topology
1 parent 7d6d2a5 commit 078aff8

9 files changed

+417
-650
lines changed

‎rtl/axicb_crossbar_top.sv‎

Lines changed: 39 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -703,15 +703,41 @@ module axicb_crossbar_top
703703

704704
localparam RCH_W = AXI_DATA_W + AXI_ID_W + 2 + RUSER_W;
705705

706-
localparam MST_ROUTES = {MST3_ROUTES,
707-
MST2_ROUTES,
708-
MST1_ROUTES,
709-
MST0_ROUTES};
710-
711-
localparam MST_OSTDREQ_NUM = {MST3_OSTDREQ_NUM[7:0],
712-
MST2_OSTDREQ_NUM[7:0],
713-
MST1_OSTDREQ_NUM[7:0],
714-
MST0_OSTDREQ_NUM[7:0]};
706+
localparam [MST_NB*SLV_NB -1:0] MST_ROUTES = {
707+
MST3_ROUTES,
708+
MST2_ROUTES,
709+
MST1_ROUTES,
710+
MST0_ROUTES};
711+
712+
localparam [2*MST_NB-1:0] MST_PRIORITY = {
713+
MST3_PRIORITY[0+:2],
714+
MST2_PRIORITY[0+:2],
715+
MST1_PRIORITY[0+:2],
716+
MST0_PRIORITY[0+:2]};
717+
718+
localparam [AXI_ID_W*MST_NB-1:0] MST_ID_MASK = {
719+
MST3_ID_MASK,
720+
MST2_ID_MASK,
721+
MST1_ID_MASK,
722+
MST0_ID_MASK};
723+
724+
localparam [MST_NB*8-1:0] MST_OSTDREQ_NUM = {
725+
MST3_OSTDREQ_NUM[7:0],
726+
MST2_OSTDREQ_NUM[7:0],
727+
MST1_OSTDREQ_NUM[7:0],
728+
MST0_OSTDREQ_NUM[7:0]};
729+
730+
parameter [AXI_ADDR_W * SLV_NB - 1:0] SLV_START_ADDR = {
731+
SLV3_START_ADDR[0+:AXI_ADDR_W],
732+
SLV2_START_ADDR[0+:AXI_ADDR_W],
733+
SLV1_START_ADDR[0+:AXI_ADDR_W],
734+
SLV0_START_ADDR[0+:AXI_ADDR_W]};
735+
736+
parameter [AXI_ADDR_W * SLV_NB - 1:0] SLV_END_ADDR = {
737+
SLV3_END_ADDR[0+:AXI_ADDR_W],
738+
SLV2_END_ADDR[0+:AXI_ADDR_W],
739+
SLV1_END_ADDR[0+:AXI_ADDR_W],
740+
SLV0_END_ADDR[0+:AXI_ADDR_W]};
715741

716742
logic [MST_NB -1:0] i_awvalid;
717743
logic [MST_NB -1:0] i_awready;
@@ -1148,24 +1174,12 @@ module axicb_crossbar_top
11481174
.MST_PIPELINE (MST_PIPELINE),
11491175
.SLV_PIPELINE (SLV_PIPELINE),
11501176
.TIMEOUT_ENABLE (TIMEOUT_ENABLE),
1151-
.MST0_ID_MASK (MST0_ID_MASK),
1152-
.MST1_ID_MASK (MST1_ID_MASK),
1153-
.MST2_ID_MASK (MST2_ID_MASK),
1154-
.MST3_ID_MASK (MST3_ID_MASK),
1177+
.MST_ID_MASK (MST_ID_MASK),
11551178
.MST_OSTDREQ_NUM (MST_OSTDREQ_NUM),
11561179
.MST_ROUTES (MST_ROUTES),
1157-
.MST0_PRIORITY (MST0_PRIORITY),
1158-
.MST1_PRIORITY (MST1_PRIORITY),
1159-
.MST2_PRIORITY (MST2_PRIORITY),
1160-
.MST3_PRIORITY (MST3_PRIORITY),
1161-
.SLV0_START_ADDR (SLV0_START_ADDR),
1162-
.SLV0_END_ADDR (SLV0_END_ADDR),
1163-
.SLV1_START_ADDR (SLV1_START_ADDR),
1164-
.SLV1_END_ADDR (SLV1_END_ADDR),
1165-
.SLV2_START_ADDR (SLV2_START_ADDR),
1166-
.SLV2_END_ADDR (SLV2_END_ADDR),
1167-
.SLV3_START_ADDR (SLV3_START_ADDR),
1168-
.SLV3_END_ADDR (SLV3_END_ADDR),
1180+
.MST_PRIORITY (MST_PRIORITY),
1181+
.SLV_START_ADDR (SLV_START_ADDR),
1182+
.SLV_END_ADDR (SLV_END_ADDR),
11691183
.AWCH_W (AWCH_W),
11701184
.WCH_W (WCH_W),
11711185
.BCH_W (BCH_W),

‎rtl/axicb_mst_switch.sv‎

Lines changed: 6 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -19,16 +19,10 @@ module axicb_mst_switch
1919
parameter TIMEOUT_ENABLE = 1,
2020

2121
// Masters ID mask
22-
parameter [AXI_ID_W-1:0] MST0_ID_MASK = 'h00,
23-
parameter [AXI_ID_W-1:0] MST1_ID_MASK = 'h10,
24-
parameter [AXI_ID_W-1:0] MST2_ID_MASK = 'h20,
25-
parameter [AXI_ID_W-1:0] MST3_ID_MASK = 'h30,
22+
parameter [AXI_ID_W*MST_NB-1:0] MST_ID_MASK = 'h30_20_10_00,
2623

2724
// Masters priorities
28-
parameter MST0_PRIORITY = 0,
29-
parameter MST1_PRIORITY = 0,
30-
parameter MST2_PRIORITY = 0,
31-
parameter MST3_PRIORITY = 0,
25+
parameter [2*MST_NB-1:0] MST_PRIORITY = 0,
3226

3327
// Channels' width (concatenated)
3428
parameter AWCH_W = 8,
@@ -85,14 +79,8 @@ module axicb_mst_switch
8579
.AXI_DATA_W (AXI_DATA_W),
8680
.MST_NB (MST_NB),
8781
.TIMEOUT_ENABLE (TIMEOUT_ENABLE),
88-
.MST0_ID_MASK (MST0_ID_MASK),
89-
.MST1_ID_MASK (MST1_ID_MASK),
90-
.MST2_ID_MASK (MST2_ID_MASK),
91-
.MST3_ID_MASK (MST3_ID_MASK),
92-
.MST0_PRIORITY (MST0_PRIORITY),
93-
.MST1_PRIORITY (MST1_PRIORITY),
94-
.MST2_PRIORITY (MST2_PRIORITY),
95-
.MST3_PRIORITY (MST3_PRIORITY),
82+
.MST_ID_MASK (MST_ID_MASK),
83+
.MST_PRIORITY (MST_PRIORITY),
9684
.AWCH_W (AWCH_W),
9785
.WCH_W (WCH_W),
9886
.BCH_W (BCH_W),
@@ -132,14 +120,8 @@ module axicb_mst_switch
132120
.AXI_DATA_W (AXI_DATA_W),
133121
.MST_NB (MST_NB),
134122
.TIMEOUT_ENABLE (TIMEOUT_ENABLE),
135-
.MST0_ID_MASK (MST0_ID_MASK),
136-
.MST1_ID_MASK (MST1_ID_MASK),
137-
.MST2_ID_MASK (MST2_ID_MASK),
138-
.MST3_ID_MASK (MST3_ID_MASK),
139-
.MST0_PRIORITY (MST0_PRIORITY),
140-
.MST1_PRIORITY (MST1_PRIORITY),
141-
.MST2_PRIORITY (MST2_PRIORITY),
142-
.MST3_PRIORITY (MST3_PRIORITY),
123+
.MST_ID_MASK (MST_ID_MASK),
124+
.MST_PRIORITY (MST_PRIORITY),
143125
.AWCH_W (AWCH_W),
144126
.WCH_W (WCH_W),
145127
.BCH_W (BCH_W),

‎rtl/axicb_mst_switch_rd.sv‎

Lines changed: 43 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -19,16 +19,10 @@ module axicb_mst_switch_rd
1919
parameter TIMEOUT_ENABLE = 1,
2020

2121
// Masters ID mask
22-
parameter [AXI_ID_W-1:0] MST0_ID_MASK = 'h00,
23-
parameter [AXI_ID_W-1:0] MST1_ID_MASK = 'h10,
24-
parameter [AXI_ID_W-1:0] MST2_ID_MASK = 'h20,
25-
parameter [AXI_ID_W-1:0] MST3_ID_MASK = 'h30,
22+
parameter [AXI_ID_W*MST_NB-1:0] MST_ID_MASK = 'h30_20_10_00,
2623

2724
// Masters priorities
28-
parameter MST0_PRIORITY = 0,
29-
parameter MST1_PRIORITY = 0,
30-
parameter MST2_PRIORITY = 0,
31-
parameter MST3_PRIORITY = 0,
25+
parameter [2*MST_NB-1:0] MST_PRIORITY = 0,
3226

3327
// Channels' width (concatenated)
3428
parameter AWCH_W = 8,
@@ -70,11 +64,7 @@ module axicb_mst_switch_rd
7064
logic [MST_NB -1:0] arch_req;
7165
logic [MST_NB -1:0] arch_grant;
7266

73-
logic mst0_rch_targeted;
74-
logic mst1_rch_targeted;
75-
logic mst2_rch_targeted;
76-
logic mst3_rch_targeted;
77-
67+
logic [MST_NB -1:0] mst_rch_targeted;
7868

7969
///////////////////////////////////////////////////////////////////////////
8070
// Read Address Channel
@@ -85,10 +75,10 @@ module axicb_mst_switch_rd
8575
axicb_round_robin
8676
#(
8777
.REQ_NB (MST_NB),
88-
.REQ0_PRIORITY (MST0_PRIORITY),
89-
.REQ1_PRIORITY (MST1_PRIORITY),
90-
.REQ2_PRIORITY (MST2_PRIORITY),
91-
.REQ3_PRIORITY (MST3_PRIORITY)
78+
.REQ0_PRIORITY (MST_PRIORITY[0*2+:2]),
79+
.REQ1_PRIORITY (MST_PRIORITY[1*2+:2]),
80+
.REQ2_PRIORITY (MST_PRIORITY[2*2+:2]),
81+
.REQ3_PRIORITY (MST_PRIORITY[3*2+:2])
9282
)
9383
arch_round_robin
9484
(
@@ -100,11 +90,14 @@ module axicb_mst_switch_rd
10090
.grant (arch_grant)
10191
);
10292

103-
assign o_arvalid = (arch_grant[0]) ? i_arvalid[0] :
104-
(arch_grant[1]) ? i_arvalid[1] :
105-
(arch_grant[2]) ? i_arvalid[2] :
106-
(arch_grant[3]) ? i_arvalid[3] :
107-
1'b0;
93+
always_comb begin
94+
95+
o_arvalid = '0;
96+
97+
for (int i=0; i<MST_NB; i++)
98+
if (arch_grant[i])
99+
o_arvalid = i_arvalid[i];
100+
end
108101

109102
assign i_arready = arch_grant & {MST_NB{o_arready}};
110103

@@ -123,38 +116,41 @@ module axicb_mst_switch_rd
123116

124117
assign arch_en = arch_en_c | arch_en_r;
125118

126-
assign o_arch = (arch_grant[0]) ? i_arch[0*ARCH_W+:ARCH_W] :
127-
(arch_grant[1]) ? i_arch[1*ARCH_W+:ARCH_W] :
128-
(arch_grant[2]) ? i_arch[2*ARCH_W+:ARCH_W] :
129-
(arch_grant[3]) ? i_arch[3*ARCH_W+:ARCH_W] :
130-
{ARCH_W{1'b0}};
119+
always_comb begin
120+
121+
o_arch = '0;
122+
123+
if (arch_grant == '0)
124+
o_arch = '0;
125+
else
126+
for (int i=0;i<MST_NB;i++)
127+
if (arch_grant[i])
128+
o_arch = i_arch[i*ARCH_W+:ARCH_W];
129+
end
131130

132131
///////////////////////////////////////////////////////////////////////////
133132
// Read Response Channel
134133
///////////////////////////////////////////////////////////////////////////
135134

136135
// RCH = {RESP, ID, DATA}
136+
generate
137+
genvar i;
138+
for (i = 0; i < MST_NB; i = i + 1) begin : MST_RCH_TARGET
139+
assign mst_rch_targeted[i] = ((MST_ID_MASK[i*AXI_ID_W+:AXI_ID_W] & o_rch[0+:AXI_ID_W]) == MST_ID_MASK[i*AXI_ID_W+:AXI_ID_W]);
140+
assign i_rvalid[i] = (mst_rch_targeted[i]) ? o_rvalid : 1'b0;
141+
assign i_rlast[i] = (mst_rch_targeted[i]) ? o_rlast : 1'b0;
142+
end
143+
endgenerate
144+
145+
always_comb begin
146+
o_rready = '0;
147+
if (mst_rch_targeted == '0)
148+
o_rready = '0;
149+
else for (int i=0; i<MST_NB; i++)
150+
if (mst_rch_targeted[i])
151+
o_rready = i_rready[i];
152+
end
137153

138-
assign mst0_rch_targeted = ((MST0_ID_MASK & o_rch[0+:AXI_ID_W]) == MST0_ID_MASK);
139-
assign mst1_rch_targeted = ((MST1_ID_MASK & o_rch[0+:AXI_ID_W]) == MST1_ID_MASK);
140-
assign mst2_rch_targeted = ((MST2_ID_MASK & o_rch[0+:AXI_ID_W]) == MST2_ID_MASK);
141-
assign mst3_rch_targeted = ((MST3_ID_MASK & o_rch[0+:AXI_ID_W]) == MST3_ID_MASK);
142-
143-
assign i_rvalid[0] = (mst0_rch_targeted) ? o_rvalid : 1'b0;
144-
assign i_rvalid[1] = (mst1_rch_targeted) ? o_rvalid : 1'b0;
145-
assign i_rvalid[2] = (mst2_rch_targeted) ? o_rvalid : 1'b0;
146-
assign i_rvalid[3] = (mst3_rch_targeted) ? o_rvalid : 1'b0;
147-
148-
assign i_rlast[0] = (mst0_rch_targeted) ? o_rlast : 1'b0;
149-
assign i_rlast[1] = (mst1_rch_targeted) ? o_rlast : 1'b0;
150-
assign i_rlast[2] = (mst2_rch_targeted) ? o_rlast : 1'b0;
151-
assign i_rlast[3] = (mst3_rch_targeted) ? o_rlast : 1'b0;
152-
153-
assign o_rready = (mst0_rch_targeted) ? i_rready[0] :
154-
(mst1_rch_targeted) ? i_rready[1] :
155-
(mst2_rch_targeted) ? i_rready[2] :
156-
(mst3_rch_targeted) ? i_rready[3] :
157-
1'b0;
158154

159155
assign i_rch = o_rch;
160156

0 commit comments

Comments
 (0)