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Cell renaming for gate level netlist simulation#24

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VJSchneid wants to merge 2 commits intogoogle:mainfrom

VJSchneid:fix_verilog_sim

Commits on Oct 21, 2025

add _func suffix for functional verilog models and rename UDP types in sequential cells
VJSchneid
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rename missing udp_hn_iq_latch primitives
VJSchneid
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