Cell renaming for gate level netlist simulation

[VJSchneid]

Hi all,

This PR (tries to) improve gate-level netlist simulation in two ways:

• It adds the _func suffix to all functional verilog models, because they are referenced in the behavioral model that way. A functional simulation should still be possible with the normal naming scheme by using the behavioral verilog files and defining FUNCTIONAL.
• All sequential cells contain an udp primitve. Those primitves seem to be provided in the models directory. However the naming of those primitves didn't match, which should be corrected now.

For me these where some issues that had to be fixed before a gate-level netlist was working. I tested my setup with an SDF-annoted simulation in Synopsys VCS. I assume that other tools should also work fine with these changes.

The following commands have been used for renaming:

find -name "*functional*.v"  -exec sed -i "s/module \(.*\)(/module \1_func(/g" {} \;
find -name "*functional*.v"  -exec sed -i "s/UDP_GF018hv5v_mcu_sc9_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP/gf180mcu_fd_sc_mcu9t5v0__udp_n_iq_ff/g" {} \;
find -name "*functional*.v"  -exec sed -i "s/UDP_GF018hv5v_mcu_sc9_TT_1P8V_25C_verilog_nonpg_MGM_N_IQ_FF_UDP/gf180mcu_fd_sc_mcu9t5v0__udp_n_iq_ff/g" {} \;
find -name "*functional*.v"  -exec sed -i "s/UDP_GF018hv5v_mcu_sc9_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP/gf180mcu_fd_sc_mcu9t5v0__udp_hn_iq_ff/g" {} \;
find -name "*functional*.v"  -exec sed -i "s/UDP_GF018hv5v_mcu_sc9_TT_1P8V_25C_verilog_nonpg_MGM_HN_IQ_FF_UDP/gf180mcu_fd_sc_mcu9t5v0__udp_hn_iq_ff/g" {} \;
find -name "*functional*.v"  -exec sed -i "s/UDP_GF018hv5v_mcu_sc9_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP/gf180mcu_fd_sc_mcu9t5v0__udp_n_iq_latch/g" {} \;
find -name "*functional*.v"  -exec sed -i "s/UDP_GF018hv5v_mcu_sc9_TT_1P8V_25C_verilog_nonpg_MGM_N_IQ_LATCH_UDP/gf180mcu_fd_sc_mcu9t5v0__udp_n_iq_latch/g" {} \;
find -name "*functional*.v"  -exec sed -i "s/UDP_GF018hv5v_mcu_sc9_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_LATCH_UDP/gf180mcu_fd_sc_mcu9t5v0__udp_hn_iq_latch/g" {} \;
find -name "*functional*.v"  -exec sed -i "s/UDP_GF018hv5v_mcu_sc9_TT_1P8V_25C_verilog_nonpg_MGM_HN_IQ_LATCH_UDP/gf180mcu_fd_sc_mcu9t5v0__udp_hn_iq_latch/g" {} \;

A similar PR for the 7-Track library is following soon ;)

[google-cla]

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[VJSchneid]

CLA is signed now. A rerun should fix the failed CI.

[RTimothyEdwards]

@VJSchneid : This repository is no longer being maintained. The PDK is being maintained here: https://github.com/fossi-foundation/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0. I believe that most issues that were caused by renaming everything from the original PDK to create the open PDK have already been resolved. Those issues that have not been resolved are taken care of by open_pdks, although those patches do need to be applied back to the repository.

[VJSchneid]

@RTimothyEdwards Thanks for pointing that out! I just briefly checked the files the repository you pointed out and it seems as if the naming issue persists there. Should I apply my fix there or is there a better way of merging it with open_pdks?

[RTimothyEdwards]

Go ahead and move the PR to the fossi-foundation repository, so that I can do a pull and check what effect it has on the open_pdks build, and what (if any) custom fixes from open_pdks can be eliminated. Open_pdks has all these custom patches because I couldn't get anything merged back into the Google repository, and then Google stopped maintaining it. Now that I have it under FOSSi Foundation ownership, I can apply those patches back to the upstream repository, finally, but I have not gotten around to doing it yet.

I am not sure what is the use of adding _func to the functional models, since from my use of the models, the functional models are simply stand-ins for the behavioral models and therefore should have the same name. I am most concerned about the suffix breaking the open_pdks installation.