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pjaaskel
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Jun 19, 2023
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Also this needs to be rebased, tested and pulled in. |
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@TopiLeppanen also this. Let's try to get these two in for the next reelase. Please describe the changes in the CHANGES doc. |
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Sure, I can do that. I don't remember why I left these. Probably was just busy at the time. |
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Rebased, and other tests pass, except these two which were also failing with main on my machine: |
Split the critical path from global lock signal to ifetch's cycle and lock counters. Registers the input to the counters, so that the global lock signal does not need to propagate entirely through the 64-bit adder.
Variants of xilinx_dp_blockram which infer BRAM on Arria 10.
Also tests the functionality of intel bram-models. (Doesn't test that they infer correctly)
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rebased to fix the CHANGES conflict |
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Some recent changes I needed to get processors generated for Intel Arria 10. These include:
Adding BRAM models that infer on Arria 10. (The old ones wouldn't infer BRAM, and the ones I add now don't infer on Xilinx :( They are just regular RTL, but the tools are very picky about the exact syntax)
Add latency to the clock cycle counter. This helped quite a lot with the clock frequency since it cuts the critical path from global_lock to the 64-bit counter.
Add wlast to AlmaIF's AXI master interface. Intel tools needed this, or it wouldn't work. The signal is hardcoded to 1, since there is no burst support from the master IF.