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AlmaIF: add tests for auto generated tb
Also tests the functionality of intel bram-models. (Doesn't test that they infer correctly)
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7 files changed

+266
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openasip/data/ProGe/tb/almaif/almaif-tb.vhdl.tmpl

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file_open(dmem_dump_file, dmem_dump_path, write_mode);
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for i in 0 to dmem_size/4-1 loop
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axi_read(dmem_start+i*4, dmem_word);
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write(line_out, integer'image(to_integer(unsigned(dmem_word))));
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write(line_out, integer'image(to_integer(signed(dmem_word))));
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writeline(dmem_dump_file, line_out);
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end loop;
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file_close(dmem_dump_file);
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DMEM size: 2048
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CQMEM size: 32768
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IMEM start: 32768
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DMEM start: 98304
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CQMEM start: 65536
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IMEM Initialization complete
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DMEM Initialization complete
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CQMEM Initialization complete
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Core done
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Output written
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#define __global__ __attribute__((address_space(5)))
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#define __param__ __attribute__((address_space(6)))
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#define __private__ __attribute__((address_space(0)))
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#include "tceops.h"
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#define N 64
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volatile __param__ int done = 0;
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__param__ char test[4]={1,2,3,4};
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volatile __param__ int results[N];
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int fib(int n)
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{
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volatile int a1=0, a2=1, retval;
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if (n <= 1)
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return n;
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for (volatile int i=0; i<n-1; ++i)
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{
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retval = a1+a2;
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a1 = a2;
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a2 = retval;
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}
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return retval;
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}
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int
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main(void)
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{
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// Force memory accesses with volatile
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for(volatile int i=0; i<N; ++i)
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{
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volatile int val = fib(i);
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volatile char* val_c = (volatile char*)(&val);
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volatile short* val_h = (volatile short*)(&val);
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volatile char temp8;
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volatile short temp16;
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// Do some byte juggling to test 16- and 8-bit accesses
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temp8 = val_c[2];
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val_c[2] = val_c[0];
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val_c[0] = temp8;
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temp8 = val_c[3];
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val_c[3] = val_c[1];
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val_c[1] = temp8;
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temp16 = val_h[1];
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val_h[1] = val_h[0];
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val_h[0] = temp16;
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results[i] = val;
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}
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done = 1;
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return 0;
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}
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#!/bin/bash
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### TCE TESTCASE
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### title: Generate a processor with AlmaIFIntegrator and integrated testbench
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TPEF=prog.tpef
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PROGE_OUT=proge-out
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ENT=almaif_core
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INTEG=AlmaIFIntegrator
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DMEM_DUMP=dmem_raw.log
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DMEM_STRIPPED=dmem_stripped.log
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TEST_NAMES=(basic_tb intel)
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while getopts "dvst:" OPTION
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do
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case $OPTION in
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d)
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leavedirty=true
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;;
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v)
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verbose=true
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;;
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s)
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spam=true
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;;
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t)
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one_test=true
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testcase=$OPTARG
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;;
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?)
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exit 1
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;;
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esac
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done
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function eexit {
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echo $1
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if [ -f compile.log ]; then cat compile.log; fi
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if [ -f sim.log ]; then cat sim.log; fi
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exit 1
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}
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function clear_test_data {
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rm -f *.img
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rm -rf $PROGE_OUT
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rm -f *.tpef
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rm -f prog_imem_pkg.vhdl
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rm -f run.log
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rm -f $DMEM_DUMP
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rm -f $DMEM_STRIPPED
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}
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function run_test {
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NAME=$1
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source test_definitions/$NAME.sh
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clear_test_data
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if [ "${spam}" == "true" ]; then
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V_SWITCH=-v
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fi
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tcecc -O3 -a $ADF -o $TPEF $SRC || eexit "tcecc failed with $SRC"
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generateprocessor -t -o $PROGE_OUT -g $INTEG -d $DMEM -f $IMEM -e $ENT \
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-p $TPEF --hdb-list=$HDBS --icd-arg-list=$ICD_ARGS \
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$EXTRA_OPT $V_SWITCH $ADF || eexit "ProGe failed with $NAME"
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generatebits -w 4 -d -e $ENT -x $PROGE_OUT -p $TPEF $EXTRA_PIG_OPTS $ADF \
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|| eexit "generatebits failed with $NAME"
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COMPLETION_SIGNAL_ADDR=$(echo "mach $ADF;prog $TPEF;symbol_address done" |\
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ttasim | head -n1)
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# If GHDL is found from PATH, compile and simulate
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GHDL=$(which ghdl 2> /dev/null)
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if [ "x${GHDL}" != "x" ]
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then
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cd $PROGE_OUT || eexit "No such dir: $PROGE_OUT"
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bash ghdl_compile.sh -v93c -a
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bash ghdl_platform_compile.sh -v93c
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bash ghdl_simulate.sh -v93c -r 10000000000 -n tta_almaif_tb \
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-g "imem_image=../prog.img" \
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-g "dmem_image=../prog_param.img" \
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-g "completion_signal_address_g=${COMPLETION_SIGNAL_ADDR}" \
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-g "log_path=../run.log" \
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-g "dmem_dump_path=../${DMEM_DUMP}"
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cd ..
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OUTPUT_BUFFER_ADDR=$(echo "mach $ADF;prog $TPEF;symbol_address results" |\
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ttasim | head -n1)
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OUTPUT_BUFFER_IDX=$((OUTPUT_BUFFER_ADDR/4))
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cat ${DMEM_DUMP} | head -n$((OUTPUT_BUFFER_IDX+64)) | tail -n 64 > $DMEM_STRIPPED
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diff run.log $HEADER || eexit "Output header didn't match for $NAME"
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diff $DMEM_STRIPPED $DATA || eexit "Output data didn't match for $NAME"
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fi
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if [ "${verbose}" == "true" ]; then
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echo "$NAME PASSED!"
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fi
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}
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if [ "${one_test}" == "true" ]; then
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run_test $testcase
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else
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for test in "${TEST_NAMES[@]}"; do
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run_test $test
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done
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fi
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if [ "${leavedirty}" != "true" ]; then
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clear_test_data
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fi
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ADF="mach/mach.adf"
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ICD_ARGS="debugger:external"
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DMEM="onchip"
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IMEM="onchip"
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SRC="src/fib_tb.c"
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HEADER="result_templates/default_header_tb.txt"
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DATA="result_templates/default_data_tb.txt"
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EXTRA_OPTS=""
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HDBS="generate_base32.hdb,generate_lsu_32.hdb,generate_rf_iu.hdb"
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ADF="mach/mach.adf"
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ICD_ARGS="debugger:external,bram-vendor:intel"
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DMEM="onchip"
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IMEM="onchip"
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SRC="src/fib_tb.c"
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HEADER="result_templates/default_header_tb.txt"
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DATA="result_templates/default_data_tb.txt"
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EXTRA_OPTS=""
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HDBS="generate_base32.hdb,generate_lsu_32.hdb,generate_rf_iu.hdb"

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