A simple risc-v single-core CPU design written in Verilog, developed for learning and practicing computer architecture and hardware description languages.
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May 28, 2026 - Verilog
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single-cycle-cpu
Here are 3 public repositories matching this topic...
CO224 Computer Architecture Labs - 8-bit Single-Cycle Processor Implementation .
instruction-set-architecture memory-hierarchy verilog-project cache-implementation single-cycle-cpu alu-design computer-architecture-and-assembly-language 8-bit-processor
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Oct 10, 2025 - Verilog
MIPS Processor Implementations (VHDL) | This repository contains multiple implementations of the MIPS (Microprocessor without Interlocked Pipelined Stages) architecture using VHDL. The project is designed for educational and academic purposes, helping students understand CPU architecture and datapath/control design. It includes Single-Cy
mips vhdl computer-organization hardware-design multi-cycle-cpu single-cycle-cpu pipelined-processor-design
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Dec 18, 2025 - VHDL
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