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Update to latest generated headers - note SVD peripherals section is now alphabetically sorted #2905

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9d16ad1
sort SVD and remove ' escapes
kilograham Apr 28, 2026
d9a1637
whitespace changes to match new generation
kilograham Apr 28, 2026
e11df67
Update to latest generated headers
kilograham Apr 28, 2026
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46,074 changes: 23,025 additions & 23,049 deletions src/rp2040/hardware_regs/RP2040.svd
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1 change: 0 additions & 1 deletion src/rp2040/hardware_regs/include/hardware/regs/adc.h
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Expand Up @@ -311,4 +311,3 @@
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_ADC_H

1 change: 0 additions & 1 deletion src/rp2040/hardware_regs/include/hardware/regs/addressmap.h
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Expand Up @@ -78,4 +78,3 @@
#define PPB_BASE _u(0xe0000000)

#endif // _ADDRESSMAP_H

1 change: 0 additions & 1 deletion src/rp2040/hardware_regs/include/hardware/regs/busctrl.h
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Expand Up @@ -324,4 +324,3 @@
#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13)
// =============================================================================
#endif // _HARDWARE_REGS_BUSCTRL_H

1 change: 0 additions & 1 deletion src/rp2040/hardware_regs/include/hardware/regs/clocks.h
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Expand Up @@ -2259,4 +2259,3 @@
#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_CLOCKS_H

972 changes: 967 additions & 5 deletions src/rp2040/hardware_regs/include/hardware/regs/dma.h
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5 changes: 2 additions & 3 deletions src/rp2040/hardware_regs/include/hardware/regs/dreq.h
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Expand Up @@ -105,13 +105,12 @@ typedef enum dreq_num_rp2040 {
DREQ_XIP_SSITX = 38, ///< Select the XIP SSI TX FIFO as DREQ
DREQ_XIP_SSIRX = 39, ///< Select the XIP SSI RX FIFO as DREQ
DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER1 as DREQ
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER2 as DREQ
DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
DREQ_FORCE = 63, ///< Select FORCE as DREQ
DREQ_COUNT
} dreq_num_t;
#endif

#endif // _DREQ_H

31 changes: 20 additions & 11 deletions src/rp2040/hardware_regs/include/hardware/regs/i2c.h
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Expand Up @@ -1960,7 +1960,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Slave-Transmitter
// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present
// 0x0 -> Slave trying to transmit to remote master in read mode-
// scenario not present
// 0x1 -> Slave trying to transmit to remote master in read mode
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000)
Expand Down Expand Up @@ -2001,8 +2002,10 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Slave-Transmitter
// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present
// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command
// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read
// command- scenario not present
// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read
// command
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13)
Expand All @@ -2019,7 +2022,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present
// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not
// present
// 0x1 -> Master or Slave-Transmitter lost arbitration
#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000)
Expand All @@ -2036,7 +2040,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
// 0x0 -> User initiating master operation when MASTER disabled- scenario not present
// 0x0 -> User initiating master operation when MASTER disabled- scenario
// not present
// 0x1 -> User initiating master operation when MASTER disabled
#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800)
Expand All @@ -2054,8 +2059,10 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Receiver
// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled
// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled
// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART
// disabled
// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART
// disabled
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10)
Expand All @@ -2080,7 +2087,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master
// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present
// 0x0 -> User trying to send START byte when RESTART disabled- scenario
// not present
// 0x1 -> User trying to send START byte when RESTART disabled
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200)
Expand All @@ -2098,7 +2106,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present
// 0x0 -> User trying to switch Master to HS mode when RESTART disabled-
// scenario not present
// 0x1 -> User trying to switch Master to HS mode when RESTART disabled
#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100)
Expand Down Expand Up @@ -2188,7 +2197,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter
// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present
// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not
// present
// 0x1 -> Transmitted data not ACKed by addressed slave
#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008)
Expand Down Expand Up @@ -2697,4 +2707,3 @@
#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_I2C_H

9 changes: 4 additions & 5 deletions src/rp2040/hardware_regs/include/hardware/regs/intctrl.h
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Expand Up @@ -55,7 +55,7 @@ typedef enum irq_num_rp2040 {
TIMER_IRQ_1 = 1, ///< Select TIMER's IRQ 1 output
TIMER_IRQ_2 = 2, ///< Select TIMER's IRQ 2 output
TIMER_IRQ_3 = 3, ///< Select TIMER's IRQ 3 output
PWM_IRQ_WRAP = 4, ///< Select PWM's IRQ_WRAP output
PWM_IRQ_WRAP = 4, ///< Select PWM's WRAP IRQ output
USBCTRL_IRQ = 5, ///< Select USBCTRL's IRQ output
XIP_IRQ = 6, ///< Select XIP's IRQ output
PIO0_IRQ_0 = 7, ///< Select PIO0's IRQ 0 output
Expand All @@ -66,14 +66,14 @@ typedef enum irq_num_rp2040 {
DMA_IRQ_1 = 12, ///< Select DMA's IRQ 1 output
IO_IRQ_BANK0 = 13, ///< Select IO_BANK0's IRQ output
IO_IRQ_QSPI = 14, ///< Select IO_QSPI's IRQ output
SIO_IRQ_PROC0 = 15, ///< Select SIO_PROC0's IRQ output
SIO_IRQ_PROC1 = 16, ///< Select SIO_PROC1's IRQ output
SIO_IRQ_PROC0 = 15, ///< Select SIO's PROC0 IRQ output
SIO_IRQ_PROC1 = 16, ///< Select SIO's PROC1 IRQ output
CLOCKS_IRQ = 17, ///< Select CLOCKS's IRQ output
SPI0_IRQ = 18, ///< Select SPI0's IRQ output
SPI1_IRQ = 19, ///< Select SPI1's IRQ output
UART0_IRQ = 20, ///< Select UART0's IRQ output
UART1_IRQ = 21, ///< Select UART1's IRQ output
ADC_IRQ_FIFO = 22, ///< Select ADC's IRQ_FIFO output
ADC_IRQ_FIFO = 22, ///< Select ADC's FIFO IRQ output
I2C0_IRQ = 23, ///< Select I2C0's IRQ output
I2C1_IRQ = 24, ///< Select I2C1's IRQ output
RTC_IRQ = 25, ///< Select RTC's IRQ output
Expand Down Expand Up @@ -121,4 +121,3 @@ typedef enum irq_num_rp2040 {
#define isr_spare_5 isr_irq31

#endif // _INTCTRL_H

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