Cleanup of inline assembly

common/include/mipscopaccess.h

@@ -0,0 +1,72 @@
+/**
+ * @file
+ * MIPS COP coprocessor access
+ */
+
+#ifndef __MIPSCOPACCESS_H__
+#define __MIPSCOPACCESS_H__
+
+#include <tamtypes.h>
+
+enum mips_cop0_reg
+{
+	/** Programmable register to select TLB entry for reading or writing (purpose: MMU) */
+	COP0_REG_Index = 0,
+	/** Pseudo-random counter for TLB replacement (purpose: MMU) */
+	COP0_REG_Random = 1,
+	/** Low half of TLB entry for even PFN (Physical page number) (purpose: MMU) */
+	COP0_REG_EntryLo0 = 2,
+	/** Low half of TLB entry for odd PFN (Physical page number) (purpose: MMU) */
+	COP0_REG_EntryLo1 = 3,
+	/** Pointer to kernel virtual PTE table (purpose: Exception) */
+	COP0_REG_Context = 4,
+	/** Mask that sets the TLB page size (purpose: MMU) */
+	COP0_REG_PageMask = 5,
+	/** Number of wired TLB entries (purpose: MMU) */
+	COP0_REG_Wired = 6,
+	/** Bad virtual address (purpose: Exception) */
+	COP0_REG_BadVAddr = 8,
+	/** Timer compare (purpose: Exception) */
+	COP0_REG_Count = 9,
+	/** High half of TLB entry(Virtual page number and ASID) (purpose: MMU) */
+	COP0_REG_EntryHi = 10,
+	/** Timer compare (purpose: Exception) */
+	COP0_REG_Compare = 11,
+	/** Processor Status Register (purpose: Exception) */
+	COP0_REG_Status = 12,
+	/** Cause of the last exception taken (purpose: Exception) */
+	COP0_REG_Cause = 13,
+	/** Exception Program Counter (purpose: Exception) */
+	COP0_REG_EPC = 14,
+	/** Processor Revision Identifier (purpose: MMU) */
+	COP0_REG_PRId = 15,
+	/** Configuration Register (purpose: MMU) */
+	COP0_REG_Config = 16,
+	/** Bad Physical Address (purpose: Exception) */
+	COP0_REG_BadPAddr = 23,
+	/** This is used for Debug function (purpose: Debug) */
+	COP0_REG_Debug = 24,
+	/** Performance Counter and Control Register (purpose: Exception) */
+	COP0_REG_Perf = 25,
+	/** Cache Tag register(low bits) (purpose: MMU) */
+	COP0_REG_TagLo = 28,
+	/** Cache Tag register(high bits) (purpose: MMU) */
+	COP0_REG_TagHi = 29,
+	/** Error Exception Program Counter (purpose: Exception) */
+	COP0_REG_ErrorPC = 30,
+};
+
+static inline __attribute__((__always_inline__)) u32 get_mips_cop_reg(const u32 cop, const u32 idx)
+{
+	u32 val;
+
+	__asm__ __volatile__("mfc%[cop]\t%[val], $%[idx]\n" : [val] "=r"(val) : [cop] "i"(cop), [idx] "i"(idx));
+	return val;
+}
+
+static inline __attribute__((__always_inline__)) void set_mips_cop_reg(const u32 cop, const u32 idx, u32 val)
+{
+	__asm__ __volatile__("mtc%[cop]\t%[val], $%[idx]\n" :: [val] "r"(val), [cop] "i"(cop), [idx] "i"(idx));
+}
+
+#endif /* __MIPSCOPACCESS_H__ */

common/sbus/src/ps2_sbus.c

@@ -26,7 +26,7 @@ static u32 _get_reg(u32 *reg)
 
 #ifdef _EE
         // EE needs 20 NOPs!
-        __asm__ volatile("nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\n");
+        __asm__ __volatile__("nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\n");
 #endif
 
         v2 = *(vu32 *)reg;

ee/debug/src/screenshot.c

@@ -250,7 +250,7 @@ int ps2_screenshot( void *pDest, unsigned int VramAdress, unsigned int x,
   *PS2SS_D1_MADR = (u32)p_dma32;
   *PS2SS_D1_CHCR = 0x101;
 
-  asm __volatile__("sync.l\n");
+  EE_SYNCL();
 
   // check if DMA is complete (STR=0)
 
@@ -272,13 +272,13 @@ int ps2_screenshot( void *pDest, unsigned int VramAdress, unsigned int x,
   *PS2SS_D1_MADR = (u32)pDest;
   *PS2SS_D1_CHCR = 0x100;
 
-  asm __volatile__(" sync.l\n");
+  EE_SYNCL();
 
   // check if DMA is complete (STR=0)
 
   while ( *PS2SS_D1_CHCR & 0x0100 );
   *PS2SS_D1_CHCR = prev_chcr;
-  asm __volatile__(" sync.l\n");
+  EE_SYNCL();
   *PS2SS_VIF1_STAT = 0;
   *PS2SS_GS_BUSDIR = (u64)0;
 

ee/dma/src/dma.c

@@ -115,8 +115,9 @@ void dma_channel_fast_waits(int channel)
 void dma_wait_fast(void)
 {
 
-	asm volatile (
-		"sync.l; sync.p;" \
+	EE_SYNCL();
+	EE_SYNCP();
+	__asm__ __volatile__ (
 		"0:" \
 		"bc0t 0f; nop;" \
 		"bc0t 0f; nop;" \

ee/elf-loader/src/elf.c

@@ -42,7 +42,7 @@ MEMORY {
 static void wipe_bramMem(void) {
 	int i;
 	for (i = 0x00084000; i < 0x100000; i += 64) {
-		asm volatile(
+		__asm__ __volatile__(
 			"\tsq $0, 0(%0) \n"
 			"\tsq $0, 16(%0) \n"
 			"\tsq $0, 32(%0) \n"

ee/elf-loader/src/loader/src/loader.c

@@ -62,7 +62,7 @@ static void wipeUserMem(void)
 {
 	int i;
 	for (i = 0x100000; i < GetMemorySize(); i += 64) {
-		asm volatile(
+		__asm__ __volatile__(
 			"\tsq $0, 0(%0) \n"
 			"\tsq $0, 16(%0) \n"
 			"\tsq $0, 32(%0) \n"

ee/graph/src/graph_mode.c

@@ -94,7 +94,7 @@ static inline int __udelay(unsigned int usecs)
 
 	}
 
-	asm volatile (
+	__asm__ __volatile__ (
 				  ".set push\n\t"
 				  ".set noreorder\n\t"
 				  "0:\n\t"
@@ -141,8 +141,8 @@ int graph_set_mode(int interlace, int mode, int ffmd, int flicker_filter)
 	GsPutIMR(0x00007700);
 
 	// Ensure registers are written prior to setting another mode.
-	asm volatile ("sync.p\n\t"
-				  "nop\n\t");
+	EE_SYNCP();
+	__asm__ __volatile__ ("nop\n\t");
 
 	// If 576P is requested, check if bios supports it.
 	if (mode == GRAPH_MODE_HDTV_576P)
@@ -376,7 +376,8 @@ void graph_set_smode1(char cmod, char gcont)
 	// Disable PRST for TV modes and enable for all other modes.
 	*GS_REG_SMODE1 = smode1_val | (u64)1 << 16;
 
-	asm volatile ("sync.l; sync.p;");
+	EE_SYNCL();
+	EE_SYNCP();
 
 	// If VESA, 1080I, or 720P, disable bit PRST now and delay 2.5ms.
 	if ((graph_crtmode >= 0x1A) && (graph_crtmode != 0x50) && (graph_crtmode != 0x53))
@@ -393,7 +394,8 @@ void graph_set_smode1(char cmod, char gcont)
 	// Now enable read circuits.
 	*GS_REG_PMODE  = pmode_val;
 
-	asm volatile ("sync.l; sync.p;");
+	EE_SYNCL();
+	EE_SYNCP();
 
 }
 

ee/kernel/include/kernel.h

@@ -20,17 +20,18 @@
 #include <stddef.h>
 #include <stdarg.h>
 #include <sifdma.h>
+#include <mipscopaccess.h>
 
 #define DI DIntr
 #define EI EIntr
 
 // Workaround for EE kernel bug: call this immediately before returning from any interrupt handler.
-#define ExitHandler() asm volatile("sync\nei\n")
+#define ExitHandler() __asm__ __volatile__("sync\nei\n")
 
 // note: 'sync' is the same as 'sync.l'
-#define EE_SYNC()  __asm__ volatile("sync")
-#define EE_SYNCL() __asm__ volatile("sync.l")
-#define EE_SYNCP() __asm__ volatile("sync.p")
+#define EE_SYNC()  __asm__ __volatile__("sync")
+#define EE_SYNCL() __asm__ __volatile__("sync.l")
+#define EE_SYNCP() __asm__ __volatile__("sync.p")
 
 #define UNCACHED_SEG(x) \
     ((void *)(((u32)(x)) | 0x20000000))
@@ -143,58 +144,37 @@ static inline void nopdelay(void)
     int i = 0xfffff;
 
     do {
-        __asm__("nop\nnop\nnop\nnop\nnop\n");
+        __asm__ __volatile__("nop\nnop\nnop\nnop\nnop\n");
     } while (i-- != -1);
 }
 
 static inline int ee_get_opmode(void)
 {
     u32 status;
 
-    __asm__ volatile(
-        ".set\tpush\n\t"
-        ".set\tnoreorder\n\t"
-        "mfc0\t%0, $12\n\t"
-        ".set\tpop\n\t"
-        : "=r"(status));
+    status = get_mips_cop_reg(0, COP0_REG_Status);
 
     return ((status >> 3) & 3);
 }
 
 static inline int ee_set_opmode(u32 opmode)
 {
-    u32 status, mask;
-
-    __asm__ volatile(
-        ".set\tpush\n\t"
-        ".set\tnoreorder\n\t"
-        "mfc0\t%0, $12\n\t"
-        "li\t%1, 0xffffffe7\n\t"
-        "and\t%0, %1\n\t"
-        "or\t%0, %2\n\t"
-        "mtc0\t%0, $12\n\t"
-        "sync.p\n\t"
-        ".set\tpop\n\t"
-        : "=r"(status), "=r"(mask)
-        : "r"(opmode));
+    u32 status;
+
+    status = (get_mips_cop_reg(0, COP0_REG_Status) & ~0x18) | opmode;
+    set_mips_cop_reg(0, COP0_REG_Status, status);
+    EE_SYNCP();
 
     return ((status >> 3) & 3);
 }
 
 static inline int ee_kmode_enter()
 {
-    u32 status, mask;
-
-    __asm__ volatile(
-        ".set\tpush\n\t"
-        ".set\tnoreorder\n\t"
-        "mfc0\t%0, $12\n\t"
-        "li\t%1, 0xffffffe7\n\t"
-        "and\t%0, %1\n\t"
-        "mtc0\t%0, $12\n\t"
-        "sync.p\n\t"
-        ".set\tpop\n\t"
-        : "=r"(status), "=r"(mask));
+    u32 status;
+
+    status = (get_mips_cop_reg(0, COP0_REG_Status) & ~0x18);
+    set_mips_cop_reg(0, COP0_REG_Status, status);
+    EE_SYNCP();
 
     return status;
 }
@@ -203,15 +183,9 @@ static inline int ee_kmode_exit()
 {
     int status;
 
-    __asm__ volatile(
-        ".set\tpush\n\t"
-        ".set\tnoreorder\n\t"
-        "mfc0\t%0, $12\n\t"
-        "ori\t%0, 0x10\n\t"
-        "mtc0\t%0, $12\n\t"
-        "sync.p\n\t"
-        ".set\tpop\n\t"
-        : "=r"(status));
+    status = get_mips_cop_reg(0, COP0_REG_Status) | 0x10;
+    set_mips_cop_reg(0, COP0_REG_Status, status);
+    EE_SYNCP();
 
     return status;
 }

ee/kernel/src/delaythread.c

@@ -17,6 +17,7 @@
 #include <timer.h>
 #include <timer_alarm.h>
 #include <delaythread.h>
+#include <mipscopaccess.h>
 
 #ifdef F_DelayThread
 static u64 DelayThreadWakeup_callback(s32 alarm_id, u64 scheduled_time, u64 actual_time, void *arg, void *pc_value)
@@ -38,7 +39,7 @@ s32 DelayThread(s32 microseconds)
 	s32 timer_alarm_id;
 	ee_sema_t sema;
 
-	__asm__ __volatile__ ("mfc0\t%0, $12" : "=r" (eie));
+	eie = get_mips_cop_reg(0, COP0_REG_Status);
 	if ((eie & 0x10000) == 0)
 	{
 		return 0x80008008; // ECPUDI