Hvdc AC emulation limits outer loop

[SylvestreSakti]

This code is largely inspired from #1048 and rebased to the current version (especially including handling of frozen HVDC Ac emulation state)

Please check if the PR fulfills these requirements

• The commit message follows our guidelines
• Tests for the changes have been added (for bug fixes / features)
• Docs have been added / updated (for bug fixes / features)
• A PR or issue has been opened in all impacted repositories (if any)

Does this PR already have an issue describing the problem?
Closes #1016

What kind of change does this PR introduce?
Change of the model to simulate HVDC AC Emulation limits

What is the current behavior?
Hvdc Ac Emulation state is handled directly in the Jacobian Matrix (depending on the state, the Equation term switches between linear mode, saturated mode or frozen mode with the corresponding derivatives). This lead in very rare cases to divergence due to zero derivative when being in saturated mode.

What is the new behavior (if this is a feature change)?
The Jacobian Matrix handles only the linear mode of AC Emulation. An outer loop checks if the AC Emulation overpasses limits and switches to fixed set point (by setting target P of VSC converters in the TargetVector).

Does this PR introduce a breaking change or deprecate an API?

• Yes
• No

This PR changes the behaviour of DC computation when HVDC emulation is on.
The saturation (PMIN/PMAX) is taken into account in DC loadflow
It is ignored in Sensitivity Analysis and fast mode DC Security Analysis

[vidaldid-rte]

Approved. PR description updated to mark it as a breaking change.

[sonarqubecloud]

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
91.2% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud