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@KastnerRG Kastner Research Group

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    76 repositories

    • particle_transformer_aie

      Public
      Python
      •1•2•0•0•Updated Apr 14, 2026Apr 14, 2026

    • fabricant-prod

      Public
      fabricant.ucsd.edu configuration
      Python
      •1•0•5•0•Updated Apr 11, 2026Apr 11, 2026

    • qualcomm-cluster

      Public
      0•0•0•0•Updated Apr 9, 2026Apr 9, 2026

    • fuzz_symbfuzz

      Public
      Python
      •
      Apache License 2.0
      •2•0•0•0•Updated Apr 6, 2026Apr 6, 2026

    • fabricant-host

      Public
      Python
      •0•0•0•0•Updated Apr 5, 2026Apr 5, 2026

    • arbolta

      Public
      Gate-level simulator for efficient hardware-software co-design.
      Rust
      •
      MIT License
      •3•0•0•0•Updated Apr 3, 2026Apr 3, 2026

    • aie4ml

      Public
      A plugin backend for hls4ml targeting AMD AI Engines (AIE)
      Python
      •
      Apache License 2.0
      •3•0•0•0•Updated Mar 31, 2026Mar 31, 2026

    • hls4ml-backend

      Public
      Python
      •0•1•0•0•Updated Mar 30, 2026Mar 30, 2026

    • hls4ml

      Public
      Machine learning on FPGAs using HLS
      Python
      •
      Apache License 2.0
      •541•2•0•0•Updated Mar 28, 2026Mar 28, 2026

    • waiter

      Public
      Waiter configurations
      Python
      •5•3•7•1•Updated Mar 28, 2026Mar 28, 2026

    • cgra4ml

      Public
      An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
      asicaifpga
      asicaifpganeural-networkcnndnnverilogsystemverilogaxi-streamasic-design
      SystemVerilog
      •
      Apache License 2.0
      •23•111•2•2•Updated Mar 26, 2026Mar 26, 2026

    • cse160-docs

      Public
      Documentation for CSE 160
      C
      •8•2•2•4•Updated Mar 22, 2026Mar 22, 2026

    • cse160-opencl-docker

      Public
      Python
      •3•1•0•2•Updated Mar 10, 2026Mar 10, 2026

    • cse160-opencl

      Public
      C++
      •2•0•0•2•Updated Mar 10, 2026Mar 10, 2026

    • yosys-SVA-AXI4_FVIP

      Public
      YosysHQ SVA AXI Properties
      SystemVerilog
      •
      ISC License
      •9•0•0•0•Updated Mar 9, 2026Mar 9, 2026

    • fuzz_presifuzz

      Public
      Pre-Silicon Hardware Fuzzing Toolkit
      Rust
      •7•0•0•0•Updated Mar 5, 2026Mar 5, 2026

    • pulp_axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      •
      Other
      •351•0•0•0•Updated Feb 21, 2026Feb 21, 2026

    • taxi

      Public
      AXI, AXI stream, Ethernet, and PCIe components in System Verilog
      SystemVerilog
      •
      CERN Open Hardware Licence Version 2 - Strongly Reciprocal
      •112•0•0•0•Updated Feb 21, 2026Feb 21, 2026

    • fuzz_hw_fuzzing_afl

      Public
      Fuzzer instrumentation for Verilog Fuzzing. Adds various coverage metrics, including Taint.
      C
      •
      Apache License 2.0
      •2•0•0•0•Updated Feb 15, 2026Feb 15, 2026

    • fuzz_hyperfuzzer

      Public
      Verilog
      •
      Other
      •2•0•0•0•Updated Feb 15, 2026Feb 15, 2026

    • fuzz_hw_like_sw

      Public
      Python
      •
      Apache License 2.0
      •11•0•0•0•Updated Feb 15, 2026Feb 15, 2026

    • fuzz_spinalfuzz

      Public
      Fuzzing for SpinalHDL
      Scala
      •
      Other
      •1•0•0•0•Updated Feb 15, 2026Feb 15, 2026

    • fuzz_fuss

      Public
      FUSS: fuzzing on a shoestring
      C++
      •
      BSD 2-Clause "Simplified" License
      •1•0•0•0•Updated Feb 15, 2026Feb 15, 2026

    • fuzz_rtl_fuzz_lab

      Public
      A Modular Open-Source Hardware Fuzzing Framework
      FIRRTL
      •
      BSD 2-Clause "Simplified" License
      •6•0•0•0•Updated Feb 15, 2026Feb 15, 2026

    • fuzz_rfuzz

      Public
      rfuzz: coverage-directed fuzzing for RTL research platform
      FIRRTL
      •
      BSD 3-Clause "New" or "Revised" License
      •14•0•0•0•Updated Feb 15, 2026Feb 15, 2026

    • fuzz_fast_hw_fuzz

      Public
      This is the source code of our submission "Bridging the Gap between Hardware Fuzzing and Industrial Verification" for GLSVLSI 2025.
      C++
      •3•0•0•0•Updated Feb 15, 2026Feb 15, 2026

    • pulp_common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •194•0•0•0•Updated Feb 6, 2026Feb 6, 2026

    • pulp_tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •42•0•0•0•Updated Feb 5, 2026Feb 5, 2026

    • pytorch_dlprim

      Public
      DLPrimitives/OpenCL out of tree backend for pytorch
      C++
      •
      MIT License
      •32•0•0•0•Updated Feb 4, 2026Feb 4, 2026

    • dlprimitives

      Public
      Deep Learning Primitives and Mini-Framework for OpenCL
      C++
      •
      MIT License
      •23•0•0•0•Updated Feb 4, 2026Feb 4, 2026
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