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Add RVC parameter to LiteX calls, doc fix #12

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Merged
meiniKi merged 6 commits into from
Apr 22, 2026
Merged

Add RVC parameter to LiteX calls, doc fix #12

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c54ef43
Update block diagram mux
meiniKi Apr 22, 2026
400c646
Add litex rvc argument documentation
meiniKi Apr 22, 2026
be126d2
Add rvc to litex_sim_test
meiniKi Apr 22, 2026
0c998bd
Automated area tracking
meiniKi Apr 22, 2026
2574247
Include logo
meiniKi Apr 22, 2026
d3cedf7
Automated area tracking
meiniKi Apr 22, 2026
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4 changes: 2 additions & 2 deletions .github/workflows/scripts/litex_sim_test.py
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ def parse_args(argv):
parser.add_argument("chunksize", type=int, help="Chunk size", choices=[1, 2, 4, 8])
parser.add_argument("conf", type=str, help="Config", choices=["MIN", "INT", "CSR"])
parser.add_argument("rftype", type=str, help="Register file type.", choices=["LOGIC", "BRAM", "BRAM_BP", "BRAM_DP", "BRAM_DP_BP"])
#parser.add_argument("rvc", type=str, help="RVC support.", choices=["NONE", "COMB", "REGS"])
parser.add_argument("rvc", type=str, help="RVC support.", choices=["NONE", "COMB", "REGS"])
return parser.parse_args(argv)

def main(argv=None):
Expand All @@ -18,7 +18,7 @@ def main(argv=None):
f"--cpu-chunksize={args.chunksize}",
f"--cpu-conf={args.conf}",
f"--cpu-rftype={args.rftype}",
#f"--cpu-rvc={args.rvc}"
f"--cpu-rvc={args.rvc}"
]

cmd = " ".join(cmd)
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3 changes: 2 additions & 1 deletion .github/workflows/verif.yml
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Expand Up @@ -65,6 +65,7 @@ jobs:
CHUNKSIZE: [8]
CONF: [MIN]
RFTYPE: [LOGIC]
RVC: [NONE, COMB]

steps:
- name: Checkout repository
Expand Down Expand Up @@ -102,7 +103,7 @@ jobs:

- name: Run LiteX sim
run: |
python .github/workflows/scripts/litex_sim_test.py ${{ matrix.CHUNKSIZE }} ${{ matrix.CONF }} ${{ matrix.RFTYPE }}
python .github/workflows/scripts/litex_sim_test.py ${{ matrix.CHUNKSIZE }} ${{ matrix.CONF }} ${{ matrix.RFTYPE }} ${{ matrix.RVC }}

riscof:
name: Run RISCOF
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4 changes: 2 additions & 2 deletions README.md
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Expand Up @@ -153,10 +153,10 @@ TARGET_ARCH=ice40 make summary.soc.all

### Litex

[LiteX](https://github.com/enjoy-digital/litex) supports FazyRV with the following options: `--cpu-chunksize` to set the chunk size (`1`, `2`, `4`, or `8`), `--cpu-conf` to set the configuration (`MIN`, `INT`, or `CSR`) and `--cpu-rftype` to set the register file type (`LOGIC`, `BRAM`, `BRAM_BP`, `BRAM_DP`, or `BRAM_DP_BP`).
[LiteX](https://github.com/enjoy-digital/litex) supports FazyRV with the following options: `--cpu-chunksize` to set the chunk size (`1`, `2`, `4`, or `8`), `--cpu-conf` to set the configuration (`MIN`, `INT`, or `CSR`), `--cpu-rftype` to set the register file type (`LOGIC`, `BRAM`, `BRAM_BP`, `BRAM_DP`, or `BRAM_DP_BP`), and `--cpu-rvc` to select support for compressed instructions (`NONE`, `COMB`, or `REG`). Note that experimental features are not supported by LiteX.

```shell
litex_sim --cpu-type=fazyrv --cpu-chunksize=4 --cpu-rftype=LOGIC
litex_sim --cpu-type=fazyrv --cpu-chunksize=4 --cpu-rftype=LOGIC --cpu-rvc=COMB
```

## Tests and Verification
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