hw/ssi/esp32_spi: fix RX bounds check and add dummy cycle handling (QEMU-282)#144
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Ahmad-myenergi wants to merge 2 commits into
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hw/ssi/esp32_spi: fix RX bounds check and add dummy cycle handling (QEMU-282)#144Ahmad-myenergi wants to merge 2 commits into
Ahmad-myenergi wants to merge 2 commits into
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The SPI TX/RX loop incorrectly used the transmitted byte value to guard buffer access instead of the loop index. This caused received bytes to be dropped when the payload value exceeded rx_bytes, breaking flash read operations. This resulted in NVS reads returning ESP_ERR_NVS_NOT_FOUND under ESP-IDF v5.5.3 when running on QEMU. Additionally, inject dummy cycles between address and data phases when SPI_USER.DUMMY is enabled to match flash fast-read behaviour expected by ESP-IDF. Reproducer: - ESP-IDF v5.5.3 - NVS set/commit/get sequence under QEMU - Fails before patch, succeeds after patch Signed-off-by: Ahmad Alhmmori <ahmad.alhmmori@myenergi.com>
Signed-off-by: Ahmad Alhmmori <ahmad.alhmmori@myenergi.com>
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Description
hw/ssi/esp32_spi, esp32c3_spi, esp32s3_spi: fix txrx buffer bounds check and add flash read dummy cycles
Problem 1 — Incorrect bounds check in
txrx_buffer(all three variants)All three ESP32 SPI controller models (
esp32_spi.c,esp32c3_spi.c,esp32s3_spi.c) contain the same bug in theirtxrx_bufferfunction:The local variable
byteholds the data being transferred, not the loop position. Using it as a bounds guard makes TX/RX behaviour depend on data values rather than byte positions. In the worst case, a received byte with a value ≥rx_bytesis silently dropped. This is a latent correctness bug in all three variants.Fix: Replace
bytewith the loop indexiin both conditions.Problem 2 — Missing dummy cycles for flash fast-read commands (
esp32_spi.conly)SPI flash fast-read commands (DOR
0x3B, Fast Read0x0B, QOR0x6B, DIOR0xBB, QIOR0xEBand their 4-byte address variants) require one dummy byte to be clocked between the address phase and the data phase. The flash chip uses those extra clock cycles to prepare its output buffer. Without them, the m25p80 flash model consumes the first real data byte as the dummy, shifting all read data by one byte.The
esp32c3_spi.candesp32s3_spi.cvariants already handle dummy cycles correctly viaesp32c3_spi_dummy_cycles()/esp32s3_spi_dummy_cycles(). The originalesp32_spi.chad no dummy phase at all.This caused NVS operations under ESP-IDF v5.5.3 to fail: every page read returned corrupted data, resulting in
ESP_ERR_NVS_NOT_FOUNDfor all stored keys.Fix: Add
esp32_spi_dummy_cycles()helper (matching the pattern in the C3/S3 variants) and call it fromesp32_spi_transaction(). In the USR command path, setdummy_bytes = 1whenSPI_USER.DUMMYis enabled and the opcode is a known flash fast-read command. PSRAM commands (which also useSPI_USER.DUMMY) are excluded as they handle dummy cycles internally in their peripheral models.Related
Testing
Checklist
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