Skip to content

refactor(boot): 收敛 RISC-V 和 LoongArch 主核启动流程#252

Merged
ZIYAN137 merged 5 commits into
mainfrom
refactor/boot-flow
May 19, 2026
Merged

refactor(boot): 收敛 RISC-V 和 LoongArch 主核启动流程#252
ZIYAN137 merged 5 commits into
mainfrom
refactor/boot-flow

Conversation

@ZIYAN137

Copy link
Copy Markdown
Contributor

变更内容

本 PR 处理 #249,主要收敛 RISC-V 和 LoongArch 中重复的主核启动流程。

  • kernel::boot 中新增 PrimaryBootOpsrun_primary_boot(),统一主核启动顺序
  • RISC-V / LoongArch boot 入口只保留架构相关 hook
  • 新增 arch::interrupts_enabled(),移除 kernel/boot.rsarch::intr 的直接依赖
  • 新增 arch::kernel::task::init_kernel_trap_frame(),避免 common boot/task 代码直接构造 TrapFrame
  • 修复 LoongArch timer CSR 配置问题
  • 修复 LoongArch 首次调度 kernel entry 时的恢复路径

验证情况

  • cargo fmt --check
  • cargo check
  • cargo check --target loongarch64-unknown-none
  • cargo build
  • cargo build --target loongarch64-unknown-none
  • kernel/boot.rs 中已无直接 TrapFrame / arch::intr 引用
  • QEMU smoke test:
    • RISC-V 可启动到 BusyBox
    • LoongArch 可进入 PID 1 并执行 /sbin/init 路径

Closes #249

ZIYAN137 added 3 commits May 19, 2026 04:43
Move common RISC-V and LoongArch primary boot steps into kernel boot code. Keep architecture boot modules focused on arch-specific hooks.
Route kernel task trap frame initialization through arch helpers. Remove direct TrapFrame construction from common task setup.
Program the LoongArch timer with the correct CSRs and restore kernel task entries directly during first schedule.
@ZIYAN137 ZIYAN137 requested a review from miiyakumo May 18, 2026 21:21

@gemini-code-assist gemini-code-assist Bot left a comment

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Code Review

This pull request unifies the primary boot sequence across architectures by introducing a generic run_primary_boot function and a PrimaryBootOps structure. It also standardizes kernel task initialization through the new init_kernel_trap_frame function and adds an interrupts_enabled method to the CpuOps trait. Review feedback identified critical copy-paste errors in the LoongArch implementation where RISC-V specific constants (SSTATUS_SIE) were used instead of the correct LoongArch CSR bits (CSR_CRMD_IE) for interrupt status checks.

Comment thread os/src/arch/loongarch/cpu_ops.rs Outdated
Comment thread os/src/arch/loongarch/cpu_ops.rs Outdated
@ZIYAN137 ZIYAN137 merged commit 62ffeda into main May 19, 2026
1 check passed
@ZIYAN137 ZIYAN137 deleted the refactor/boot-flow branch May 19, 2026 16:57
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

启动流程重构:抽取 RISC-V/LoongArch boot 共同逻辑

1 participant