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CLA
CLA
 
 
MUL
MUL
 
 
TB
TB
 
 
Altomari_Giulio_Giovanni___Relazione_progetto_di_Reti_Logiche.pdf
Altomari_Giulio_Giovanni___Relazione_progetto_di_Reti_Logiche.pdf
 
 
BIAS_SUBTRACTOR.vhd
BIAS_SUBTRACTOR.vhd
 
 
DECODER_2_4.vhd
DECODER_2_4.vhd
 
 
DENORMALIZER.vhd
DENORMALIZER.vhd
 
 
EDGE_CASES_HANDLER.vhd
EDGE_CASES_HANDLER.vhd
 
 
EXP_ADDER.vhd
EXP_ADDER.vhd
 
 
FA.vhd
FA.vhd
 
 
FINAL_EXP_CALCULATOR.vhd
FINAL_EXP_CALCULATOR.vhd
 
 
FIRST_STAGE.vhd
FIRST_STAGE.vhd
 
 
FLAG_SETTER.vhd
FLAG_SETTER.vhd
 
 
Full architecture.pdf
Full architecture.pdf
 
 
MANTIX_FIXER.vhd
MANTIX_FIXER.vhd
 
 
NORMALIZER.vhd
NORMALIZER.vhd
 
 
OFFSET_ENCODER.vhd
OFFSET_ENCODER.vhd
 
 
OPERANDS_SPLITTER.vhd
OPERANDS_SPLITTER.vhd
 
 
OUTPUT_LOGIC.vhd
OUTPUT_LOGIC.vhd
 
 
README.md
README.md
 
 
REG_PP_1.vhd
REG_PP_1.vhd
 
 
REG_PP_32.vhd
REG_PP_32.vhd
 
 
REG_PP_N.vhd
REG_PP_N.vhd
 
 
RESULT_FIXER.vhd
RESULT_FIXER.vhd
 
 
ROUNDER.vhd
ROUNDER.vhd
 
 
SECOND_STAGE.vhd
SECOND_STAGE.vhd
 
 
TEST_FINALE.vhd
TEST_FINALE.vhd
 
 
THIRD_STAGE.vhd
THIRD_STAGE.vhd
 
 

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IEEE-754-Multiplier-Project

This is a project made for Politecnico di Milano, for the Logic Networks course.

In this project I've recreated the structure of a multiplier, following the IEEE 754 standard. The project has been developed and tested in Vivado, written in VHDL.

The relation is only available in italian. Final Grading: 30/30.

Milky zani piz (those who know: :O ciao piaggio)

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This is a project made for Politecnico di Milano, for the Logic Networks course.

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polimipolimi-notespolimi-projectpolimi-projectsvhdl

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