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hardware: Update ElemRV
* Use new Clock and Reset Controllers * Use Edge enum instead of string * Move power and ground IO cells to top-level class * Rework clock handling Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
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4 files changed

+304
-163
lines changed

4 files changed

+304
-163
lines changed

‎hardware/scala/elemrv_h/ECPIX5/ECPIX5.scala‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -88,9 +88,10 @@ case class ECPIX5Top() extends Component {
8888
ResetParameter("system", 128),
8989
ResetParameter("debug", 128)
9090
)
91+
val inputClock = ClockParameter("input", ECPIX5.SystemClock.frequency, "input")
9192
val clocks = List[ClockParameter](
9293
ClockParameter("system", 50 MHz, "system"),
93-
ClockParameter("debug", 10 MHz, "debug", synchronousWith = "system")
94+
ClockParameter("debug", 12.5 MHz, "debug", synchronousWith = "system")
9495
)
9596
val kitParameter = KitParameter(resets, clocks)
9697
val boardParameter = ECPIX5.Parameter(kitParameter, ECPIX5.SystemClock.frequency)
@@ -99,14 +100,20 @@ case class ECPIX5Top() extends Component {
99100
socParameter,
100101
8 kB,
101102
8 MB,
102-
(resetCtrl: ResetControllerCtrl, _, clock: Bool) => { resetCtrl.buildXilinx(clock) },
103-
(clockCtrl: ClockControllerCtrl, resetCtrl: ResetControllerCtrl, clock: Bool) => {
104-
clockCtrl.buildLatticeECP5Pll(
105-
clock,
106-
resetCtrl,
107-
boardParameter.getOscillatorFrequency,
103+
(parameter: ResetControllerCtrl.Parameter) => {
104+
val resetCtrl = new ResetControllerCtrl.GeneratorResetController(parameter)
105+
resetCtrl
106+
},
107+
(
108+
parameter: ClockControllerCtrl.Parameter,
109+
resetCtrl: ResetControllerCtrl.ResetControllerBase
110+
) => {
111+
val clockCtrl = new ClockControllerCtrl.LatticeECP5PllController(
112+
parameter,
113+
inputClock,
108114
List("system", "debug")
109115
)
116+
clockCtrl
110117
},
111118
(parameter: BmbParameter, ramSize: BigInt) => {
112119
val ram = BmbIhpOnChipRam.OnePort1Macro(parameter, ramSize.toInt)

‎hardware/scala/elemrv_h/SG13G2/SG13G2.scala‎

Lines changed: 65 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,9 @@ import spinal.lib._
1010
import spinal.lib.bus.bmb._
1111

1212
import nafarr.system.reset._
13-
import nafarr.system.reset.ResetControllerCtrl._
1413
import nafarr.system.clock._
15-
import nafarr.system.clock.ClockControllerCtrl._
1614
import nafarr.blackboxes.ihp.sg13g2._
15+
import nafarr.blackboxes.ihp.common._
1716
import nafarr.memory.ocram.ihp.sg13g2.BmbIhpOnChipRam
1817

1918
import zibal.misc._
@@ -83,9 +82,10 @@ case class SG13G2Top() extends Component {
8382
ResetParameter("system", 128),
8483
ResetParameter("debug", 128)
8584
)
85+
val inputClock = ClockParameter("input", 50 MHz, "input")
8686
val clocks = List[ClockParameter](
8787
ClockParameter("system", 50 MHz, "system"),
88-
ClockParameter("debug", 10 MHz, "debug", synchronousWith = "system")
88+
ClockParameter("debug", 12.5 MHz, "debug", synchronousWith = "system")
8989
)
9090
val kitParameter = KitParameter(resets, clocks)
9191
val boardParameter = ElemRVBoard.Parameter(kitParameter)
@@ -94,11 +94,20 @@ case class SG13G2Top() extends Component {
9494
socParameter,
9595
8 kB,
9696
8 MB,
97-
(resetCtrl: ResetControllerCtrl, reset: Bool, _) => {
98-
resetCtrl.buildDummy(reset)
97+
(parameter: ResetControllerCtrl.Parameter) => {
98+
val resetCtrl = new ResetControllerCtrl.DummyResetController(parameter)
99+
resetCtrl
99100
},
100-
(clockCtrl: ClockControllerCtrl, resetCtrl: ResetControllerCtrl, clock: Bool) => {
101-
clockCtrl.buildDummy(clock, resetCtrl)
101+
(
102+
parameter: ClockControllerCtrl.Parameter,
103+
resetCtrl: ResetControllerCtrl.ResetControllerBase
104+
) => {
105+
val clockCtrl = new ClockControllerCtrl.ClockDividerController(
106+
parameter,
107+
inputClock,
108+
List("system", "debug")
109+
)
110+
clockCtrl
102111
},
103112
(parameter: BmbParameter, ramSize: BigInt) => {
104113
val ram = BmbIhpOnChipRam.OnePort1Macro(parameter, ramSize.toInt)
@@ -107,39 +116,39 @@ case class SG13G2Top() extends Component {
107116
)
108117

109118
val io = new Bundle {
110-
val clock = IhpCmosIo("south", 5)
111-
val reset = IhpCmosIo("south", 4, "clk_main")
119+
val clock = IhpCmosIo(Edge.South, 5)
120+
val reset = IhpCmosIo(Edge.South, 4, "clk_main")
112121
val jtag = new Bundle {
113-
val tms = IhpCmosIo("south", 0, "clk_jtag")
114-
val tdi = IhpCmosIo("south", 1, "clk_jtag")
115-
val tdo = IhpCmosIo("south", 2, "clk_jtag")
116-
val tck = IhpCmosIo("south", 3, "clk_jtag")
122+
val tms = IhpCmosIo(Edge.South, 0, "clk_jtag")
123+
val tdi = IhpCmosIo(Edge.South, 1, "clk_jtag")
124+
val tdo = IhpCmosIo(Edge.South, 2, "clk_jtag")
125+
val tck = IhpCmosIo(Edge.South, 3)
117126
}
118127
val spi = new Bundle {
119128
val cs = Vec(
120-
IhpCmosIo("east", 0, "clk_main")
129+
IhpCmosIo(Edge.East, 0, "clk_main")
121130
)
122-
val sck = IhpCmosIo("east", 1, "clk_main")
131+
val sck = IhpCmosIo(Edge.East, 1, "clk_main")
123132
val dq = Vec(
124-
IhpCmosIo("east", 5, "clk_main"),
125-
IhpCmosIo("east", 4, "clk_main"),
126-
IhpCmosIo("east", 3, "clk_main"),
127-
IhpCmosIo("east", 2, "clk_main")
133+
IhpCmosIo(Edge.East, 5, "clk_main"),
134+
IhpCmosIo(Edge.East, 4, "clk_main"),
135+
IhpCmosIo(Edge.East, 3, "clk_main"),
136+
IhpCmosIo(Edge.East, 2, "clk_main")
128137
)
129138
}
130139
val pins = Vec(
131-
IhpCmosIo("west", 2, "clk_main"),
132-
IhpCmosIo("west", 3, "clk_main"),
133-
IhpCmosIo("west", 4, "clk_main"),
134-
IhpCmosIo("west", 5, "clk_main"),
135-
IhpCmosIo("west", 6, "clk_main"),
136-
IhpCmosIo("west", 7, "clk_main"),
137-
IhpCmosIo("north", 2, "clk_main"),
138-
IhpCmosIo("north", 3, "clk_main"),
139-
IhpCmosIo("north", 4, "clk_main"),
140-
IhpCmosIo("north", 5, "clk_main"),
141-
IhpCmosIo("north", 6, "clk_main"),
142-
IhpCmosIo("north", 7, "clk_main")
140+
IhpCmosIo(Edge.West, 2, "clk_main"),
141+
IhpCmosIo(Edge.West, 3, "clk_main"),
142+
IhpCmosIo(Edge.West, 4, "clk_main"),
143+
IhpCmosIo(Edge.West, 5, "clk_main"),
144+
IhpCmosIo(Edge.West, 6, "clk_main"),
145+
IhpCmosIo(Edge.West, 7, "clk_main"),
146+
IhpCmosIo(Edge.North, 2, "clk_main"),
147+
IhpCmosIo(Edge.North, 3, "clk_main"),
148+
IhpCmosIo(Edge.North, 4, "clk_main"),
149+
IhpCmosIo(Edge.North, 5, "clk_main"),
150+
IhpCmosIo(Edge.North, 6, "clk_main"),
151+
IhpCmosIo(Edge.North, 7, "clk_main")
143152
)
144153
}
145154

@@ -165,10 +174,16 @@ case class SG13G2Top() extends Component {
165174
io.pins(index) <> IOPadInOut4mA(soc.io.pins.pins(index))
166175
}
167176

168-
for (index <- 0 until 2) { IOPadIOVdd() }
169-
for (index <- 0 until 2) { IOPadIOVss() }
170-
for (index <- 0 until 2) { IOPadVdd() }
171-
for (index <- 0 until 2) { IOPadVss() }
177+
val power = Seq(
178+
IhpPowerIo(Edge.South, 6, IhpPowerIoCell.SG13G2.Vss),
179+
IhpPowerIo(Edge.South, 7, IhpPowerIoCell.SG13G2.Vdd),
180+
IhpPowerIo(Edge.East, 6, IhpPowerIoCell.SG13G2.IOVdd),
181+
IhpPowerIo(Edge.East, 7, IhpPowerIoCell.SG13G2.IOVss),
182+
IhpPowerIo(Edge.North, 0, IhpPowerIoCell.SG13G2.Vss),
183+
IhpPowerIo(Edge.North, 1, IhpPowerIoCell.SG13G2.Vdd),
184+
IhpPowerIo(Edge.West, 0, IhpPowerIoCell.SG13G2.IOVdd),
185+
IhpPowerIo(Edge.West, 1, IhpPowerIoCell.SG13G2.IOVss)
186+
)
172187
}
173188

174189
object SG13G2Generate extends ElementsApp {
@@ -181,30 +196,33 @@ object SG13G2Generate extends ElementsApp {
181196
}
182197

183198
val chip = OpenROADTools.IHP.Config(elementsConfig, OpenROADTools.PDKs.IHP.sg13g2)
184-
chip.dieArea = (0, 0, 1881.6, 1882.44)
185-
chip.coreArea = (394.08, 396.9, 1484.64, 1485.54)
199+
chip.dieArea = (0, 0, 2081.28, 2079)
200+
chip.coreArea = (394.08, 396.9, 1684.32, 1682.1)
186201
chip.hasIoRing = true
187202
chip.addMacro(
188203
report.toplevel.soc.system.onChipRam.ctrl.asInstanceOf[BmbIhpOnChipRam.OnePort1Macro].ram,
189204
444.96,
190205
448.35,
191-
"MX"
206+
"MX",
207+
depth = 3
192208
)
193-
194209
chip.addClock(report.toplevel.io.clock.PAD, 50 MHz, "clk_main")
195210
chip.addClock(report.toplevel.io.jtag.tck.PAD, 10 MHz, "clk_jtag")
211+
chip.addGeneratedClock(
212+
report.toplevel.io.clock.PAD,
213+
report.toplevel.inputClock.frequency,
214+
"clk_debug",
215+
report.toplevel.soc.clockCtrl.io.clocks,
216+
report.toplevel.soc.clockCtrl.getPortIndexByName("debug"),
217+
report.toplevel.soc.clockCtrl.getClockDomainByName("debug").frequency.getValue
218+
)
219+
chip.addReset(report.toplevel.io.reset.PAD)
196220
chip.setFalsePath("clk_main", "clk_jtag")
221+
chip.setFalsePath("clk_system", "clk_jtag")
197222
chip.io = Some(report.toplevel.io)
223+
chip.ioPower = Some(report.toplevel.power)
198224
chip.pdnRingWidth = 30.0
199225
chip.pdnRingSpace = 5.0
200-
chip.addPad("south", 6, "sg13g2_IOPadVss")
201-
chip.addPad("south", 7, "sg13g2_IOPadVdd")
202-
chip.addPad("east", 6, "sg13g2_IOPadIOVdd")
203-
chip.addPad("east", 7, "sg13g2_IOPadIOVss")
204-
chip.addPad("north", 0, "sg13g2_IOPadVss")
205-
chip.addPad("north", 1, "sg13g2_IOPadVdd")
206-
chip.addPad("west", 0, "sg13g2_IOPadIOVdd")
207-
chip.addPad("west", 1, "sg13g2_IOPadIOVss")
208226
chip.generate
209227
}
210228

‎hardware/scala/elemrv_n/ECPIX5/ECPIX5.scala‎

Lines changed: 26 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,7 @@ import spinal.lib._
1111
import spinal.lib.bus.bmb._
1212

1313
import nafarr.system.reset._
14-
import nafarr.system.reset.ResetControllerCtrl._
1514
import nafarr.system.clock._
16-
import nafarr.system.clock.ClockControllerCtrl._
1715
import nafarr.blackboxes.lattice.ecp5._
1816
import nafarr.memory.ocram.ihp.sg13g2.BmbIhpOnChipRam
1917

@@ -64,8 +62,10 @@ case class ECPIX5Board() extends Component {
6462
w956a8mbya.io.ckN := analogFalse
6563
for (index <- 0 until top.io.hyperbus.dq.length) {
6664
w956a8mbya.io.dqIn(index) := io.hyperbus.dq(index)
65+
io.hyperbus.dq(index).addTag(crossClockDomain)
6766
io.hyperbus.dq(index) := w956a8mbya.io.dqOut(index)
6867
}
68+
w956a8mbya.io.rwdsIn.addTag(crossClockDomain)
6969
w956a8mbya.io.rwdsIn := io.hyperbus.rwds
7070
io.hyperbus.rwds := w956a8mbya.io.rwdsOut
7171
w956a8mbya.io.csN := io.hyperbus.cs(0)
@@ -74,8 +74,9 @@ case class ECPIX5Board() extends Component {
7474
top.io.hyperbus.cs(1).PAD := analogFalse
7575
top.io.hyperbus.cs(2).PAD := analogFalse
7676
top.io.hyperbus.cs(3).PAD := analogFalse
77+
top.io.hyperbus.ckN.PAD := analogFalse
78+
top.io.hyperbus.ck.PAD := top.io.hyperbus.ck.PAD
7779
io.hyperbus.cs(0) := top.io.hyperbus.cs(0).PAD
78-
io.hyperbus.ck := top.io.hyperbus.ck.PAD
7980
io.hyperbus.reset := top.io.hyperbus.reset.PAD
8081
io.hyperbus.rwds <> top.io.hyperbus.rwds.PAD
8182
for (index <- 0 until top.io.hyperbus.dq.length) {
@@ -118,11 +119,16 @@ case class ECPIX5Top() extends Component {
118119
val resets = List[ResetParameter](
119120
ResetParameter("system", 128),
120121
ResetParameter("cpu", 128),
122+
ResetParameter("hyperbus", 128),
123+
ResetParameter("spiXip", 128),
121124
ResetParameter("debug", 128)
122125
)
126+
val inputClock = ClockParameter("input", ECPIX5.SystemClock.frequency, "input")
123127
val clocks = List[ClockParameter](
124-
ClockParameter("system", 20 MHz, "system"),
125-
ClockParameter("cpu", 20 MHz, "cpu", synchronousWith = "system"),
128+
ClockParameter("system", 50 MHz, "system"),
129+
ClockParameter("cpu", 50 MHz, "cpu", synchronousWith = "system"),
130+
ClockParameter("hyperbus", 100 MHz, "hyperbus"),
131+
ClockParameter("spiXip", 100 MHz, "spiXip"),
126132
ClockParameter("debug", 10 MHz, "debug", synchronousWith = "system")
127133
)
128134
val hyperbusPartitions = List[(BigInt, Boolean)](
@@ -139,14 +145,20 @@ case class ECPIX5Top() extends Component {
139145
4 kB,
140146
8 MB,
141147
hyperbusPartitions,
142-
(resetCtrl: ResetControllerCtrl, _, clock: Bool) => { resetCtrl.buildXilinx(clock) },
143-
(clockCtrl: ClockControllerCtrl, resetCtrl: ResetControllerCtrl, clock: Bool) => {
144-
clockCtrl.buildLatticeECP5Pll(
145-
clock,
146-
resetCtrl,
147-
boardParameter.getOscillatorFrequency,
148-
List("system", "cpu", "debug")
148+
(parameter: ResetControllerCtrl.Parameter) => {
149+
val resetCtrl = new ResetControllerCtrl.GeneratorResetController(parameter)
150+
resetCtrl
151+
},
152+
(
153+
parameter: ClockControllerCtrl.Parameter,
154+
resetCtrl: ResetControllerCtrl.ResetControllerBase
155+
) => {
156+
val clockCtrl = new ClockControllerCtrl.ClockDividerController(
157+
parameter,
158+
inputClock,
159+
List("system", "cpu", "hyperbus", "spiXip", "debug")
149160
)
161+
clockCtrl
150162
},
151163
(parameter: BmbParameter, ramSize: BigInt) => {
152164
val ram = BmbIhpOnChipRam.OnePort1Macro(parameter, ramSize.toInt)
@@ -278,6 +290,7 @@ case class ECPIX5Top() extends Component {
278290
done := True
279291
}
280292
}
293+
soc.io_plat.reset := spiReset.done
281294
io.spi.rst <> FakeO(spiReset.done)
282295

283296
for (index <- 0 until 3) {
@@ -307,8 +320,7 @@ object ECPIX5Generate extends ElementsApp {
307320
object ECPIX5Simulate extends ElementsApp {
308321
val compiled = elementsConfig.genFPGASimConfig.compile {
309322
val board = ECPIX5Board()
310-
BinTools.initRam(board.spiNor.deviceOut.data, elementsConfig.swStorageBaremetalImage("bootrom"))
311-
BinTools.initRam(board.w956a8mbya.device.data, elementsConfig.swStorageBaremetalImage("demo"))
323+
BinTools.initRam(board.spiNor.deviceOut.data, elementsConfig.swStorageImageContainer)
312324
for (domain <- board.top.soc.parameter.getKitParameter.clocks) {
313325
board.top.soc.clockCtrl.getClockDomainByName(domain.name).clock.simPublic()
314326
}

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