Update Taskfile

* Fix some style-guide issues
* Add bondpads while the generator script is not ready
* Move firmware and fpga commands to namespaces

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>

Author: dnltz

README.rst

@@ -72,13 +72,13 @@ Start by generating the necessary files for the ECPIX5 Board, then synthesize th
 
 .. code-block:: text
 
-    task fpga-prepare fpga-synthesize
+    task fpga:prepare fpga:synthesize
 
 Next, program the ECP5 FPGA with the synthesized bitstream.
 
 .. code-block:: text
 
-    task fpga-flash
+    task fpga:flash
 
 ASIC Flow
 #########

REUSE.toml

@@ -19,3 +19,8 @@ SPDX-License-Identifier = "CERN-OHL-W-2.0"
 path = "software/*/spi.layout"
 SPDX-FileCopyrightText = "2025 aesc silicon"
 SPDX-License-Identifier = "Apache-2.0"
+
+[[annotations]]
+path = "tmp/*/*"
+SPDX-FileCopyrightText = "2026 aesc silicon"
+SPDX-License-Identifier = "CERN-OHL-W-2.0"

Taskfile.firmware.yml

@@ -0,0 +1,25 @@
+# SPDX-FileCopyrightText: 2026 aesc silicon
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+# yaml-language-server: $schema=https://taskfile.dev/schema.json
+
+version: '3'
+
+tasks:
+  compile:
+    desc: Compiles bare metal firmwares.
+    cmds:
+      - task: ':lib-baremetal-firmware'
+        vars:
+         board: "{{.TECH}}"
+         app: "bootrom"
+      - task: ':lib-baremetal-firmware'
+        vars:
+         board: "{{.TECH}}"
+         app: "demo"
+      - "{{ .RUN }} './software/{{ .package }}/gen_image_container.sh'"
+
+  flash:
+    desc: Programs the SPI flash with the compiled firmware image.
+    cmds:
+      - "flashrom -p buspirate_spi:dev=/dev/serial/by-id/usb-Bus_Pirate_Bus_Pirate_5_5buspirate-if02,spispeed=8M -c MT25QL256 -l software/{{ .package }}/spi.layout -i flash -n -w {{ .BUILD_ROOT}}/{{ .SOC }}/{{ .TECH }}/firmware/image_container.img"

Taskfile.fpga.yml

@@ -0,0 +1,50 @@
+# SPDX-FileCopyrightText: 2026 aesc silicon
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+# yaml-language-server: $schema=https://taskfile.dev/schema.json
+
+version: '3'
+
+tasks:
+  default:
+    desc: Runs the full FPGA flow - prepare, synthesize, and flash.
+    cmds:
+      - task: prepare
+      - task: synthesize
+      - task: flash
+
+  prepare:
+    desc: Produces the Verilog file and metadata needed for FPGA operations.
+    cmds:
+      - task: ':lib-generate'
+        vars:
+          board: "ECPIX5"
+
+  synthesize:
+    desc: Generates the FPGA bitstream by synthesizing the design.
+    cmds:
+      - task: ':lib-synthesize-fpga'
+        vars:
+          board: "ECPIX5"
+          vendor: "Lattice"
+
+  flash:
+    desc: Programs the FPGA with the generated bitstream.
+    cmds:
+      - task: ':lib-flash-bitstream'
+        vars:
+          board: "ECPIX5"
+
+  simulate:
+    desc: Runs simulations at the RTL level. Add 'duration=n' to specify the duration in n milliseconds.
+    cmds:
+      - task: ':lib-simulate'
+        vars:
+          board: "ECPIX5"
+
+  view-simulation:
+    desc: Opens the simulation with GTKWave.
+    cmds:
+      - task: ':lib-view-simulation'
+        vars:
+          board: "ECPIX5"

Taskfile.yml

@@ -1,6 +1,7 @@
 # SPDX-FileCopyrightText: 2025 aesc silicon
 #
 # SPDX-License-Identifier: CERN-OHL-W-2.0
+# yaml-language-server: $schema=https://taskfile.dev/schema.json
 
 version: '3'
 
@@ -9,187 +10,158 @@ includes:
     taskfile: ./modules/elements/zibal/Taskfile.yaml
     optional: true
     flatten: true
-
-env:
-  FPGA_FAMILY: ecp5
-  FPGA_DEVICE: um5g-45k
-  FPGA_PACKAGE: CABGA554
-  FPGA_FREQUENCY: 50
-  OPENFPGALOADER_BOARD: ecpix5_r03
-  PDK: ihp-sg13g2
-  PDK_ROOT: "{{ .PWD }}/pdks/IHP-Open-PDK/"
-  KLAYOUT_HOME: "{{ .PWD }}/pdks/IHP-Open-PDK/ihp-sg13g2/libs.tech/klayout/"
-  NAFARR_BASE: "{{ .PWD }}/modules/elements/nafarr/"
-  ZIBAL_BASE: "{{ .PWD }}/modules/elements/zibal/"
-  BUILD_ROOT: "{{ .PWD }}/build/"
-  GCC: "/opt/elements/zephyr-sdk-0.17.0/riscv64-zephyr-elf/bin/riscv64-zephyr-elf"
-  OPENROAD_FLOW_ROOT: "{{ .PWD }}/tools/OpenROAD-flow-scripts/flow"
+  firmware:
+    taskfile: ./Taskfile.firmware.yml
+  fpga:
+    taskfile: ./Taskfile.fpga.yml
 
 vars:
   SOC: '{{.SOC | default "ElemRV-N"}}'
+  TECH: '{{.TECH | default "SG13G2"}}'
   package:
     sh: echo "{{.SOC}}" | tr '[:upper:]' '[:lower:]' | tr '-' '_'
+  PDK:
+    sh: echo "ihp-{{.TECH}}" | tr '[:upper:]' '[:lower:]'
+  KLAYOUT_HOME: "{{.PWD}}/pdks/IHP-Open-PDK/{{.PDK}}/libs.tech/klayout/"
   CONTAINER_NAME: elemrv_container
   CONTAINER_ENV: " \
-    -e SOC={{ .SOC }} \
-    -e FPGA_FAMILY={{ .FPGA_FAMILY }} \
-    -e FPGA_DEVICE={{ .FPGA_DEVICE }} \
-    -e FPGA_PACKAGE={{ .FPGA_PACKAGE }} \
-    -e FPGA_FREQUENCY={{ .FPGA_FREQUENCY }} \
-    -e PDK={{ .PDK }} \
-    -e PDK_ROOT={{ .PDK_ROOT }} \
-    -e KLAYOUT_HOME={{ .KLAYOUT_HOME }} \
-    -e NAFARR_BASE={{ .NAFARR_BASE }} \
-    -e ZIBAL_BASE={{ .ZIBAL_BASE }} \
-    -e BUILD_ROOT={{ .BUILD_ROOT }} \
-    -e GCC={{ .GCC }} \
+    -e SOC={{.SOC}} \
+    -e TECH={{.TECH}} \
+    -e FPGA_FAMILY={{.FPGA_FAMILY}} \
+    -e FPGA_DEVICE={{.FPGA_DEVICE}} \
+    -e FPGA_PACKAGE={{.FPGA_PACKAGE}} \
+    -e FPGA_FREQUENCY={{.FPGA_FREQUENCY}} \
+    -e PDK={{.PDK}} \
+    -e PDK_ROOT={{.PDK_ROOT}} \
+    -e KLAYOUT_HOME={{.KLAYOUT_HOME}} \
+    -e NAFARR_BASE={{.NAFARR_BASE}} \
+    -e ZIBAL_BASE={{.ZIBAL_BASE}} \
+    -e VEXRISCV_ROOT={{.VEXRISCV_ROOT}} \
+    -e BUILD_ROOT={{.BUILD_ROOT}} \
+    -e GCC={{.GCC}} \
 "
 
+env:
+  FPGA_FAMILY: ecp5
+  FPGA_DEVICE: um5g-45k
+  FPGA_PACKAGE: CABGA554
+  FPGA_FREQUENCY: 50
+  OPENFPGALOADER_BOARD: ecpix5_r03
+  PDK_ROOT: "{{.PWD}}/pdks/IHP-Open-PDK/"
+  NAFARR_BASE: "{{.PWD}}/modules/elements/nafarr/"
+  ZIBAL_BASE: "{{.PWD}}/modules/elements/zibal/"
+  VEXRISCV_ROOT: "{{.PWD}}/modules/elements/vexriscv/"
+  BUILD_ROOT: "{{.PWD}}/build/"
+  GCC: "/opt/elements/zephyr-sdk-0.17.0/riscv64-zephyr-elf/bin/riscv64-zephyr-elf"
+  OPENROAD_FLOW_ROOT: "{{.PWD}}/tools/OpenROAD-flow-scripts/flow"
 
 tasks:
-  project-prepare:
-    desc: Sets up a virtual environment, installs tools, and initializes project dependencies.
+  _project-prepare:
     cmds:
       - virtualenv venv
       - venv/bin/pip3 install podman-compose==1.0.6
       - curl https://storage.googleapis.com/git-repo-downloads/repo > repo
       - chmod a+rx repo
-      - ./repo init -u https://github.com/aesc-silicon/ElemRV.git -b {{if .branch}}{{.branch}}{{else}}main{{end}} -m manifest{{if .nightly}}-nightly{{end}}.xml
+      - ./repo init -u https://github.com/aesc-silicon/ElemRV.git -b {{if .branch}}{{.branch}}{{else}}main{{end}} -m manifest{{.manifest_suffix}}.xml
 
-  build-container:
-    desc: Creates a container with all necessary host requirements pre-installed.
+  _build-container:
     cmds:
-      - venv/bin/podman-compose build
+      - venv/bin/podman-compose {{if .CI}}--podman-pull-args=-q{{end}} pull
+
   repo-sync:
     desc: Downloads and synchronizes all required dependencies.
     cmds:
-      - ./repo sync
+      - ./repo sync {{if .CI}}-q{{end}}
+
   install:
     desc: Installs all dependencies and prepares the project for FPGA and chip workflows.
     cmds:
-      - task: project-prepare
-      - task: build-container
+      - task: _project-prepare
+      - task: _build-container
       - task: repo-sync
     vars:
       branch: "main"
-      nightly: "false"
-
-  fpga-prepare:
-    desc: Produces the Verilog file and metadata needed for FPGA operations.
-    cmds:
-      - task: lib-generate
-        vars:
-          board: "ECPIX5"
-  fpga-synthesize:
-    desc: Generates the FPGA bitstream by synthesizing the design.
-    cmds:
-      - task: lib-synthesize-fpga
-        vars:
-          board: "ECPIX5"
-          vendor: "Lattice"
-  fpga-flash:
-    desc: Programs the FPGA with the generated bitstream.
-    cmds:
-      - task: lib-flash-bitstream
-        vars:
-          board: "ECPIX5"
-  fpga-simulate:
-    desc: Runs simulations at the RTL level. Add 'duration=n' to specify the duration in n milliseconds.
-    cmds:
-      - task: lib-simulate
-        vars:
-          board: "ECPIX5"
-  fpga-view-simulation:
-    desc: Opens the simulation with GTKWave.
-    cmds:
-      - task: lib-view-simulation
-        vars:
-          board: "ECPIX5"
-
-  compile-firmware:
-     desc: Compiles bare metal firmwares.
-     cmds:
-       - task: lib-baremetal-firmware
-         vars:
-          board: "SG13G2"
-          app: "bootrom"
-       - task: lib-baremetal-firmware
-         vars:
-          board: "SG13G2"
-          app: "demo"
+      manifest_suffix: ""
 
   prepare:
     desc: Generates all necessary source files and metadata for chip layout creation.
     cmds:
       - task: lib-generate
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
       - task: lib-sealring
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
+      - "mkdir -p {{.BUILD_ROOT}}/{{.SOC}}/{{.TECH}}/zibal/macros/bondpad"
+      - "cp tmp/{{.PDK}}/bondpad_70x70.lef {{.BUILD_ROOT}}/{{.SOC}}/{{.TECH}}/zibal/macros/bondpad/"
+      - "cp tmp/{{.PDK}}/bondpad_70x70.gds.gz {{.BUILD_ROOT}}/{{.SOC}}/{{.TECH}}/zibal/macros/bondpad/bondpad_70x70.gds.gz"
+      # TODO: wait until bondpad.py got fixed
+      #- task: lib-bondpad
+      #  vars:
+      #    board: "{{.TECH}}"
 
   simulate:
     desc: Runs simulations at the RTL level. Add 'duration=n' to specify the duration in n milliseconds.
     cmds:
       - task: lib-simulate
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   view-simulation:
     desc: Opens the simulation with GTKWave.
     cmds:
       - task: lib-view-simulation
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   layout:
     desc: Creates the physical layout of the chip.
     cmds:
       - task: lib-layout
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   filler:
     desc: Inserts filler cells into the layout to ensure proper chip functionality.
     cmds:
       - task: lib-filler
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   run-drc:
     desc: Performs Design Rule Checks and reports violations; use 'level=minimal' for a basic check.
     cmds:
       - task: lib-run-drc
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   view-drc:
     desc: Displays DRC results in KLayout; 'level=minimal' opens minimal deck results.
     cmds:
       - task: lib-view-drc
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   view-openroad:
     desc: Loads the layout into OpenROAD for further analysis or modification.
     cmds:
       - task: lib-view-openroad
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   view-klayout:
     desc: Opens the chip layout in KLayout for inspection.
     cmds:
       - task: lib-view-klayout
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   check-logs:
     desc: Checks the build directory for warnings or errors in the logs.
     cmds:
       - task: lib-check-logs
         vars:
-          board: "SG13G2"
+          board: "{{.TECH}}"
 
   default:
     desc: Executes the full IHP SG13G2 RTL-to-GDSII flow and validates the layout afterwards.

tmp/ihp-sg13cmos5l/bondpad_70x70.gds.gz

@@ -0,0 +1,36 @@
+VERSION 5.8 ;
+
+MACRO bondpad_70x70
+  CLASS COVER ;
+  ORIGIN 0 0 ;
+  FOREIGN bondpad_70x70 0 0 ;
+  SIZE 70.0 BY 70.0 ;
+  SYMMETRY X Y R90 ;
+  SITE sg13cmos5l_ioSite ;
+  PIN pad
+    USE SIGNAL ;
+    PORT
+      LAYER Metal2 ;
+        RECT 0 0 70.0 70.0 ;
+      LAYER Metal3 ;
+        RECT 0 0 70.0 70.0 ;
+      LAYER Metal4 ;
+        RECT 0 0 70.0 70.0 ;
+      LAYER TopMetal1 ;
+        RECT 0 0 70.0 70.0 ;
+    END
+  END pad
+
+  OBS
+    LAYER Metal1 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER Metal2 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER Metal3 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER Metal4 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER TopMetal1 ;
+      RECT 0 0 70.0 70.0 ;
+  END
+END bondpad_70x70