UsartSpi Support

avr-hal-generic/src/lib.rs

@@ -21,6 +21,7 @@ pub mod port;
 pub mod simple_pwm;
 pub mod spi;
 pub mod usart;
+pub mod usart_spi;
 pub mod wdt;
 
 /// Prelude containing all HAL traits

avr-hal-generic/src/usart_spi.rs

@@ -0,0 +1,95 @@
+//! MSPIM Implimentation
+use crate::spi;
+
+// This module just impliments a macro for SpiOps, since underlyingly, the Spi type can still be used since it just needs SpiOps
+
+pub type UsartSpi<H, USART, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> =
+    spi::Spi<H, USART, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>;
+
+// Impliment SpiOps trait for USART
+#[macro_export]
+macro_rules! add_usart_spi {
+    (
+        hal: $HAL:ty,
+        peripheral: $USART_SPI:ty,
+        register_suffix: $n:expr,
+        sclk: $sclkpin:ty,
+        mosi: $mosipin:ty,
+        miso: $misopin:ty,
+        cs: $cspin:ty,
+    ) => {
+        $crate::paste::paste! {
+            // This is quite a messy way to get the doc string working properly... but it works!
+            #[doc = concat!("**Clock:** `", stringify!($sclkpin), "`<br>**MOSI:** `", stringify!($mosipin), "`<br> **MISO:** `", stringify!($misopin), "`<br> **CS:** `", stringify!($cspin), "`")]
+            pub type [<Usart $n Spi>] = avr_hal_generic::usart_spi::UsartSpi<$HAL, $USART_SPI, $sclkpin, $mosipin, $misopin, $cspin>;
+
+            impl $crate::spi::SpiOps<$HAL, $sclkpin, $mosipin, $misopin, $cspin> for $USART_SPI {
+                fn raw_setup(&mut self, settings: &crate::spi::Settings) {
+                    use $crate::hal::spi;
+
+                    // Setup control registers
+                    // We start by setting the UBBRn to 0
+                    self.[<ubrr $n>].write(|w| unsafe {w.bits(0)});
+
+                    // We have to translate the character size register into the 2 bits which are the MSB/LSB and the phase
+                    // 5 Bit Char = MSB and 1st
+                    // 6 Bit Char = MSB and 2nd
+                    // 7 Bit Char = LSB and 1st
+                    // 8 Bit Char = LSB and 2nd
+                    self.[<ucsr $n c>].write(|w| {
+                        w.[<umsel $n>]().spi_master();
+
+                        match settings.data_order {
+                            crate::spi::DataOrder::MostSignificantFirst => match settings.mode.phase {
+                                spi::Phase::CaptureOnFirstTransition => w.[<ucsz $n>]().chr5(),
+                                spi::Phase::CaptureOnSecondTransition => w.[<ucsz $n>]().chr6(),
+                            },
+                            crate::spi::DataOrder::LeastSignificantFirst => match settings.mode.phase {
+                                spi::Phase::CaptureOnFirstTransition => w.[<ucsz $n>]().chr7(),
+                                spi::Phase::CaptureOnSecondTransition => w.[<ucsz $n>]().chr8(),
+                            },
+                        };
+
+                        match settings.mode.polarity {
+                            spi::Polarity::IdleLow => w.[<ucpol $n>]().clear_bit(),
+                            spi::Polarity::IdleHigh => w.[<ucpol $n>]().set_bit(),
+                        }
+                    });
+
+                    // Enable receiver and transmitter, and also the rec interrupt.
+                    self.[<ucsr $n b>].write(|w| w
+                        .[<txen $n>]().set_bit()
+                        .[<rxen $n>]().set_bit()
+                        .[<rxcie $n>]().set_bit()
+                    );
+
+                    // Set the baudrate of the UBRRn, idk what it should be set to, so for now, it'll be set to 0
+                    self.[<ubrr $n>].write(|w| unsafe{w.bits(0)});
+                }
+
+                fn raw_release(&mut self) {
+                    // Probably a better way to "release" the SPI interface, but from the datasheet, this is what they suggest, so ig it works
+                    self.[<ucsr $n c>].write(|w| w.[<umsel $n>]().usart_async());
+                }
+
+                fn raw_check_iflag(&self) -> bool {
+                    self.[<ucsr $n a>].read().[<rxc $n>]().bit_is_set()
+                }
+
+                fn raw_read(&self) -> u8 {
+                    self.[<udr $n>].read().bits()
+                }
+
+                fn raw_write(&mut self, byte: u8) {
+                    self.[<udr $n>].write(|w| unsafe { w.bits(byte) });
+                }
+
+                fn raw_transaction(&mut self, byte: u8) -> u8 {
+                    self.raw_write(byte);
+                    while !self.raw_check_iflag() {}
+                    self.raw_read()
+                }
+            }
+        }
+    };
+}

examples/atmega2560/src/bin/atmega2560-usart_spi-feedback.rs

@@ -0,0 +1,78 @@
+//! This example demonstrates how to set up a SPI interface and communicate
+//! over it.  The physical hardware configuration consists of connecting a
+//! jumper directly from pin `PB2` to pin `PB3`.
+//!
+//! Run the program using `cargo run`.
+//! You should see it output the line `data: 42` repeatedly.
+//! If the output you see is `data: 255`, you may need to check your jumper.
+
+#![no_std]
+#![no_main]
+
+use atmega_hal::delay::Delay;
+use atmega_hal::usart::{Baudrate, Usart};
+use atmega_hal::usart_spi;
+use embedded_hal::delay::DelayNs;
+use embedded_hal::spi::SpiBus;
+use panic_halt as _;
+
+// Define core clock. This can be used in the rest of the project.
+type CoreClock = atmega_hal::clock::MHz16;
+
+#[avr_device::entry]
+fn main() -> ! {
+    let dp = atmega_hal::Peripherals::take().unwrap();
+    let pins = atmega_hal::pins!(dp);
+
+    let mut delay = Delay::<crate::CoreClock>::new();
+
+    // set up serial interface for text output
+    let mut serial = Usart::new(
+        dp.USART0,
+        pins.pe0,
+        pins.pe1.into_output(),
+        Baudrate::<crate::CoreClock>::new(57600),
+    );
+
+    // Create SPI interface.
+    let (mut spi, _) = usart_spi::Usart1Spi::new(
+        dp.USART1,
+        pins.pd5.into_output(),
+        pins.pd3.into_output(),
+        pins.pd2.into_pull_up_input(),
+        pins.pd4.into_output().downgrade(),
+        atmega_hal::spi::Settings::default(),
+    );
+
+    /* Other SPI examples for other USART's
+       let (mut spi, _) = usart_spi::Usart2Spi::new(
+           dp.USART2,
+           pins.ph2.into_output(),
+           pins.ph1.into_output(),
+           pins.ph0.into_pull_up_input(),
+           pins.pd4.into_output().downgrade(),
+           atmega_hal::spi::Settings::default(),
+       );
+
+       let (mut spi, _) = usart_spi::Usart3Spi::new(
+           dp.USART3,
+           pins.pj2.into_output(),
+           pins.pj1.into_output(),
+           pins.pj0.into_pull_up_input(),
+           pins.pd4.into_output().downgrade(),
+           atmega_hal::spi::Settings::default(),
+       );
+    */
+
+    loop {
+        // Send a byte
+        let data_out: [u8; 1] = [42];
+        let mut data_in: [u8; 1] = [0];
+        // Send a byte
+        // Because MISO is connected to MOSI, the read data should be the same
+        spi.transfer(&mut data_in, &data_out).unwrap();
+
+        ufmt::uwriteln!(&mut serial, "data: {}\r", data_in[0]).unwrap();
+        delay.delay_ms(1000);
+    }
+}

mcu/atmega-hal/src/lib.rs

@@ -145,6 +145,9 @@ pub mod eeprom;
 #[cfg(feature = "device-selected")]
 pub use eeprom::Eeprom;
 
+#[cfg(feature = "device-selected")]
+pub mod usart_spi;
+
 pub struct Atmega;
 
 #[cfg(any(feature = "atmega48p", feature = "atmega168", feature = "atmega328p"))]

mcu/atmega-hal/src/usart.rs

@@ -14,7 +14,8 @@ pub type UsartReader<USART, RX, TX, CLOCK> =
     feature = "atmega328p",
     feature = "atmega328pb",
     feature = "atmega1284p",
-    feature = "atmega164pa"
+    feature = "atmega164pa",
+    feature = "atmega48p"
 ))]
 pub type Usart0<CLOCK> = Usart<
     crate::pac::USART0,
@@ -27,7 +28,8 @@ pub type Usart0<CLOCK> = Usart<
     feature = "atmega328p",
     feature = "atmega328pb",
     feature = "atmega1284p",
-    feature = "atmega164pa"
+    feature = "atmega164pa",
+    feature = "atmega48p"
 ))]
 avr_hal_generic::impl_usart_traditional! {
     hal: crate::Atmega,

mcu/atmega-hal/src/usart_spi.rs

@@ -0,0 +1,104 @@
+//! USART MSPIM implimentations
+//!
+//! The following list details how many USARTs and if the USARTs support MSPIM for each board choosable.
+//!
+//! | Board | USARTs | SPI |
+//! |-------|--------|-----|
+//! | `atmega48p` | 1 | Yes |
+//! | `atmega164pa`| 2 | Yes |
+//! | `atmega168` | 1 | Yes |
+//! | `atmega328p` | 1 | Yes |
+//! | `atmega328pb` | 1 | Yes |
+//! | `atmega32a` | 1 | No |
+//! | `atmega32u4` | 1 | Yes |
+//! | `atmega2560` | 4 | Yes |
+//! | `atmega128a` | 2 | No |
+//! | `atmega1280` | 4 | Yes |
+//! | `atmega1284p` | 2 | Yes |
+//! | `atmega8` | 1 | No |
+
+// Supress warning because it doesn't recognise us using it in macros properly.
+#[allow(unused_imports)]
+use crate::port;
+
+#[cfg(any(feature = "atmega1280", feature = "atmega2560"))]
+avr_hal_generic::add_usart_spi! {
+    hal: crate::Atmega,
+    peripheral: crate::pac::USART0,
+    register_suffix: 0,
+    sclk: port::PE2,
+    mosi: port::PE1,
+    miso: port::PE0,
+    cs: port::Dynamic,
+}
+
+#[cfg(any(feature = "atmega1280", feature = "atmega2560"))]
+avr_hal_generic::add_usart_spi! {
+    hal: crate::Atmega,
+    peripheral: crate::pac::USART1,
+    register_suffix: 1,
+    sclk: port::PD5,
+    mosi: port::PD3,
+    miso: port::PD2,
+    cs: port::Dynamic,
+}
+
+#[cfg(any(feature = "atmega1280", feature = "atmega2560"))]
+avr_hal_generic::add_usart_spi! {
+    hal: crate::Atmega,
+    peripheral: crate::pac::USART2,
+    register_suffix: 2,
+    sclk: port::PH2,
+    mosi: port::PH1,
+    miso: port::PH0,
+    cs: port::Dynamic,
+}
+
+#[cfg(any(feature = "atmega1280", feature = "atmega2560"))]
+avr_hal_generic::add_usart_spi! {
+    hal: crate::Atmega,
+    peripheral: crate::pac::USART3,
+    register_suffix: 3,
+    sclk: port::PJ2,
+    mosi: port::PJ1,
+    miso: port::PJ0,
+    cs: port::Dynamic,
+}
+
+#[cfg(any(
+    feature = "atmega168",
+    feature = "atmega328p",
+    feature = "atmega328pb",
+    feature = "atmega48p"
+))]
+avr_hal_generic::add_usart_spi! {
+    hal: crate::Atmega,
+    peripheral: crate::pac::USART0,
+    register_suffix: 0,
+    sclk: port::PD4,
+    mosi: port::PD1,
+    miso: port::PD0,
+    cs: port::Dynamic,
+}
+
+#[cfg(any(feature = "atmega1284p", feature = "atmega164pa",))]
+avr_hal_generic::add_usart_spi! {
+    hal: crate::Atmega,
+    peripheral: crate::pac::USART0,
+    register_suffix: 0,
+    sclk: port::PB0,
+    mosi: port::PD1,
+    miso: port::PD0,
+    cs: port::Dynamic,
+}
+
+#[cfg(any(feature = "atmega1284p", feature = "atmega164pa",))]
+avr_hal_generic::add_usart_spi! {
+    hal: crate::Atmega,
+    peripheral: crate::pac::USART1,
+    register_suffix: 1,
+    sclk: port::PD4,
+    mosi: port::PD3,
+    miso: port::PD2,
+    cs: port::Dynamic,
+}