gr-heep.core

CAPI=2:

# Copyright 2025 X-HEEP
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

name: x-heep:systems:gr-heep
description: GR-HEEP extended SoC (from X-HEEP).

filesets:
  files_rtl_generic:
    depend:
    - x-heep::packages
    - x-heep:ip:pad_control
    - openhwgroup.org:systems:core-v-mini-mcu
    files:
    - hw/gr-heep/gr_heep_pkg.sv
    - hw/gr-heep/gr_heep_xbar.sv
    - hw/gr-heep/gr_heep_bus.sv
    - hw/gr-heep/gr_heep_pad_ring.sv
    - hw/gr-heep/gr_heep_peripherals.sv
    - hw/gr-heep/gr_heep.sv
    file_type: systemVerilogSource

  # Simulation
  files_verilator_waiver:
    files:
    - hw/gr-heep/gr_heep_waivers.vlt
    - tb/tb.vlt
    - tb/tb_v5.vlt
    file_type: vlt

  tb-verilator:
    files:
    - tb/XHEEP_CmdLineOptions.hh: { is_include_file: true }
    - tb/XHEEP_CmdLineOptions.cpp
    - tb/tb_top.cpp
    file_type: cppSource

  tb-harness:
    depend:
    - pulp-platform.org::tech_cells_generic
    - x-heep:sim:sram_wrapper
    - x-heep:sim:pad_cells
    files:
    - tb/tb_util.svh: {is_include_file: true}
    - tb/yosys_spiflash.sv
    - tb/testharness.sv
    file_type: systemVerilogSource

  tb-sv:
    files:
    - tb/tb_top.sv
    file_type: systemVerilogSource

  uartdpi:
    depend:
    - lowrisc:dv_dpi:uartdpi

  systemverilog_only_uart:
    files:
    - hw/vendor/x-heep/hw/vendor/lowrisc/opentitan/hw/dv/dpi/uartdpi/uartdpi.sv
    file_type: systemVerilogSource

  systemverilog_only_simjtag:
    depend:
    - pulp-platform.org::pulpissimo_simjtag

  # FPGA
  rtl-fpga:
    depend:
    - openhwgroup.org:systems:core-v-mini-mcu-fpga
    files:
    - hw/fpga_ext/xilinx_gr_heep_wrapper.sv
    file_type: systemVerilogSource

  # Scripts for hooks
  pre_build_remote_bitbang:
    files:
    - scripts/sim/compile_remote_bitbang.sh
    file_type: user

  pre_build_uartdpi:
    files:
    - scripts/sim/compile_uart_dpi.sh
    file_type: user

  pre_patch_modelsim_Makefile:
    files:
    - hw/vendor/x-heep/scripts/sim/modelsim/patch_modelsim_Makefile.py
    file_type: user

parameters:
  JTAG_DPI:
    datatype: int
    paramtype: vlogparam
    description: |
      Enables testbench JTAG DIPs. Admitted values: 1|0.
    default: 0
  USE_EXTERNAL_DEVICE_EXAMPLE:
    datatype: int
    paramtype: vlogparam
    description: |
      Enables testbench modules compilation. Admitted values: 1|0.
    default: 1
  USE_UPF:
    datatype: bool
    paramtype: vlogdefine
    description: |
      Enables simulation with UPF with Modelsim/VCS
  REMOVE_OBI_FIFO:
    datatype: bool
    paramtype: vlogdefine
    description: |
      Remove the FIFO between the BUS and the peripherals subsystems
  SYNTHESIS:
    datatype: bool
    paramtype: vlogdefine
    default: false
  VERILATOR: #used by SV2V
    datatype: bool
    paramtype: vlogdefine
    default: false
  SIM_SYSTEMC:
    datatype: bool
    paramtype: vlogdefine
    default: false
  FPGA_SYNTHESIS:
    datatype: bool
    paramtype: vlogdefine
    default: false
  FPGA_NEXYS:
    datatype: bool
    paramtype: vlogdefine
    default: false
  FPGA_ZCU104:
    datatype: bool
    paramtype: vlogdefine
    default: false
  FPGA_ZCU102:
    datatype: bool
    paramtype: vlogdefine
    default: false
  FPGA_AUP_ZU3:
    datatype: bool
    paramtype: vlogdefine
    default: false
  FPGA_GENESYS2:
    datatype: bool
    paramtype: vlogdefine
    default: false
  NO_DDR_CLK_PORTS:
    datatype: bool
    paramtype: vlogdefine
    default: false
  # Make the parameter known to FuseSoC to enable overrides from the
  # command line. If not overwritten, use the generic technology library.
  PRIM_DEFAULT_IMPL:
    datatype: str
    paramtype: vlogdefine
    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
    default: prim_pkg::ImplGeneri
  COMMON_CELLS_ASSERTS_OFF:
    datatype: bool
    description: Turn off asserts for PULP common cells
    paramtype: vlogdefine
    default: false
  ASSERTS_OFF:
    datatype: bool
    description: Turn off asserts for PULP common cells
    paramtype: vlogdefine
    default: false

scripts:
  # Build utils
  pre_build_remote_bitbang:
    cmd:
    - sh
    - ../../../scripts/sim/compile_remote_bitbang.sh
  pre_build_uartdpi:
    cmd:
    - sh
    - ../../../scripts/sim/compile_uart_dpi.sh
  pre_patch_modelsim_Makefile:
    cmd:
    - python
    - ../../../hw/vendor/x-heep/scripts/sim/modelsim/patch_modelsim_Makefile.py

  # Simulation utils
  remove_uart_log:
    cmd: [sh, -c, rm -f uart0.log]
  print_uart_log:
    cmd: [sh, -c, cat uart0.log]

targets:
  default: &default_target
    filesets:
    - files_rtl_generic
    - target_sim? (tool_verilator? (files_verilator_waiver))
    toplevel: [gr_heep]

  sim:
    <<: *default_target
    default_tool: modelsim
    filesets_append:
    - tb-harness
    - tool_verilator? (uartdpi)
    - tool_verilator? (tb-verilator)
    - tool_verilator? (systemverilog_only_simjtag)
    - tool_modelsim? (systemverilog_only_uart)
    - tool_modelsim? (tb-sv)
    - tool_modelsim? (systemverilog_only_simjtag)
    - tool_modelsim? (pre_build_remote_bitbang)
    - tool_modelsim? (pre_build_uartdpi)
    - tool_modelsim? (pre_patch_modelsim_Makefile)
    toplevel:
    - tool_verilator? (testharness)
    - tool_modelsim? (tb_top)
    hooks:
      pre_build:
        - tool_modelsim? (pre_build_uartdpi)
        - tool_modelsim? (pre_build_remote_bitbang)
        - tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
      pre_run:
        - remove_uart_log
      post_run:
        - print_uart_log
    parameters:
    - JTAG_DPI
    - USE_EXTERNAL_DEVICE_EXAMPLE
    - USE_UPF
    - REMOVE_OBI_FIFO
    - COMMON_CELLS_ASSERTS_OFF
    - ASSERTS_OFF
    tools:
      verilator:
        mode: cc
        verilator_options:
          - '--cc'
          - '--trace'
          - '--trace-fst'
          - '--trace-structs'
          - '--trace-params'
          - '--trace-max-array 1024'
          - '--x-assign unique'
          - '--x-initial unique'
          - '--exe tb_top.cpp'
          - '-CFLAGS "-Wall -fpermissive"'
          - '-LDFLAGS "-pthread -lutil -lelf"'
          - "-Wall"
      modelsim:
        vlog_options:
        - -override_timescale 1ns/1ps
        - -suppress vlog-2583
        - -suppress vlog-2577
        - -suppress vlog-2720
        - -pedanticerrors
        - -define MODELSIM
        vsim_options:
        - -sv_lib ../../../hw/vendor/x-heep/hw/vendor/lowrisc/opentitan/hw/dv/dpi/uartdpi/uartdpi
        - -sv_lib ../../../hw/vendor/x-heep/hw/vendor/pulp_platform/pulpissimo/rtl/tb/remote_bitbang/librbs
        - -voptargs=+acc=npr

  pynq-z2:
    <<: *default_target
    default_tool: vivado
    description: TUL Pynq-Z2 Board
    filesets_append:
    - rtl-fpga
    parameters:
    - SYNTHESIS=true
    - REMOVE_OBI_FIFO
    - FPGA_SYNTHESIS=true
    tools:
      vivado:
        part: xc7z020clg400-1
        board_part: tul.com.tw:pynq-z2:part0:1.0
        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_pynq_z2_board_files]
    toplevel: [xilinx_gr_heep_wrapper]

  nexys-a7-100t:
    <<: *default_target
    default_tool: vivado
    description: Digilent Nexys-A7-100T Board
    filesets_append:
    - rtl-fpga
    parameters:
    - SYNTHESIS=true
    - REMOVE_OBI_FIFO
    - FPGA_SYNTHESIS=true
    - FPGA_NEXYS=true
    - NO_DDR_CLK_PORTS=true
    tools:
      vivado:
        part: xc7a100tcsg324-1
        board_part: digilentinc.com:nexys-a7-100t:part0:1.3
        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files]
    toplevel: [xilinx_gr_heep_wrapper]

  zcu104:
    <<: *default_target
    default_tool: vivado
    description: ZCU104 Evaluation Board
    filesets_append:
    - rtl-fpga
    parameters:
    - SYNTHESIS=true
    - REMOVE_OBI_FIFO
    - FPGA_SYNTHESIS=true
    - FPGA_ZCU104=true
    - NO_DDR_CLK_PORTS=true
    tools:
      vivado:
        part: xczu7ev-ffvc1156-2-e
        board_part: xilinx.com:zcu104:part0:1.0
        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files]
    toplevel: [xilinx_gr_heep_wrapper]

  zcu102:
    <<: *default_target
    default_tool: vivado
    description: ZCU102 Evaluation Board
    filesets_append:
    - rtl-fpga
    parameters:
    - SYNTHESIS=true
    - REMOVE_OBI_FIFO
    - FPGA_SYNTHESIS=true
    - FPGA_ZCU102=true
    - NO_DDR_CLK_PORTS=true
    tools:
      vivado:
        part: xczu9eg-ffvb1156-2-e
        board_part: xilinx.com:zcu102:part0:3.3
        board_repo_paths: [../../../hw/fpga/board_files/vendor/zcu102]
    toplevel: [xilinx_gr_heep_wrapper]

  aup-zu3:
    <<: *default_target
    default_tool: vivado
    description: RD aup-zu3 Board
    filesets_append:
    - rtl-fpga
    parameters:
    - SYNTHESIS=true
    - REMOVE_OBI_FIFO
    - FPGA_SYNTHESIS=true
    - FPGA_AUP_ZU3=true
    - NO_DDR_CLK_PORTS=true
    tools:
      vivado:
        part: xczu3eg-sfvc784-2-e
        board_part: realdigital.org:aup-zu3-8gb:part0:1.0
        board_repo_paths: [../../../hw/fpga/board_files/vendor/aup-zu3-8gb/1.0]
    toplevel: [xilinx_gr_heep_wrapper]

  genesys2:
    <<: *default_target
    default_tool: vivado
    description: Genesys2 Evaluation Board
    filesets_append:
    - rtl-fpga
    parameters:
    - SYNTHESIS=true
    - REMOVE_OBI_FIFO
    - FPGA_SYNTHESIS=true
    - FPGA_GENESYS2=true
    - NO_DDR_CLK_PORTS=true
    tools:
      vivado:
        part: xc7k325tffg900-2
        board_part: digilentinc.com:genesys2:part0:1.1
        board_repo_paths: [../../../hw/fpga/board_files/vendor/genesys2]
    toplevel: [xilinx_gr_heep_wrapper]