include working mxgen

Author: Rakanic

.gitmodules

@@ -7,6 +7,6 @@
 [submodule "software/gemmini-rocc-tests"]
 	path = software/gemmini-rocc-tests
 	url = https://github.com/Rakanic/gemmini-rocc-tests.git
-[submodule "src/main/scala/gemmini/mxgen"]
-	path = src/main/scala/gemmini/mxgen
+[submodule "mxgen"]
+	path = mxgen
 	url = git@github.com:ucb-bar/MxGen.git

build.sbt

@@ -6,6 +6,25 @@ version := "3.1.0"
 
 scalaVersion := "2.13.10"
 
+// Belt-and-suspenders exclusion of files inside the mxgen submodule that sbt
+// shouldn't compile as part of gemmini's main classpath:
+//   - mxgen/test/**       : mill-style test sources (depend on scalatest/chiseltest)
+//   - mxgen/out/**        : mill's transient build output (re-generates each mill invocation)
+//   - mxgen/.../Main.scala: standalone Verilog emitter (App entry point)
+def mxgenStaleFile(f: java.io.File): Boolean = {
+  val p = f.getAbsolutePath.replace('\\', '/')
+  p.contains("/mxgen/test/") ||
+  p.contains("/mxgen/out/") ||
+  p.endsWith("/mxgen/src/main/scala/mxgen/Main.scala")
+}
+
+Compile / unmanagedSources / excludeFilter ~= { prev =>
+  prev || new sbt.io.SimpleFileFilter(f => mxgenStaleFile(f))
+}
+
+Compile / unmanagedSources := (Compile / unmanagedSources).value.filterNot(mxgenStaleFile)
+Compile / sources          := (Compile / sources).value.filterNot(mxgenStaleFile)
+
 // libraryDependencies ++= Seq(
 //   "edu.berkeley.cs" %% "chisel3" % "3.6.0",
 //   "edu.berkeley.cs" %% "rocketchip" % "1.2.+",

mxgen

@@ -0,0 +1,6 @@
+// mxgen lives as a sibling of this directory (at <gemmini>/mxgen). Its sources
+// are not under sbt's scalaSource walk, so they have to be added explicitly.
+// Only src/main/scala is included — the mill workspace, tests, and Main.scala
+// (in elab/) stay invisible to sbt.
+Compile / unmanagedSourceDirectories +=
+  baseDirectory.value.getParentFile / "mxgen" / "src" / "main" / "scala"

src/build.sbt

@@ -7,6 +7,7 @@ import freechips.rocketchip.tile.FType
 import chisel3._
 import chisel3.util._
 import hardfloat._
+import mxgen.{MxConfig, MxFormat, MxTypeBundle, requiredPEMode}
 
 // Bundles that represent the raw bits of custom datatypes
 case class Float(expWidth: Int, sigWidth: Int, isRecoded: Boolean = false) extends Bundle {
@@ -630,16 +631,22 @@ object Arithmetic {
 
       override def mac_mx(m1: MxFloat, m2: MxFloat, fpProductPrecision: (Int, Int), fpAccPrecision: MxFloat, activation_mx_format: UInt, weight_mx_format: UInt): MxFloat = {
         require(!m1.isRecoded && !m2.isRecoded) // mxFloat inputs must be in standard format
-        val macc = Module(new MxFpMul(lut = false)(fpProductPrecision, fpAccPrecision))
+        val macConfig = MxConfig.mxGemmini.copy(
+          inActBusWidth    = m1.bits.getWidth,
+          inWeiBusWidth    = m2.bits.getWidth,
+          productFormat    = MxFormat(fpProductPrecision._1, fpProductPrecision._2),
+          accFormat        = MxFormat(fpAccPrecision.expWidth, fpAccPrecision.sigWidth)
+        )
+        val macc = Module(new mxgen.MxFpMul(macConfig, lut = false))
         val result = Wire(MxFloat(macc.cType.exp, macc.cType.sig, 4, true))
 
-        val typeA = Wire(new MxTypes)
+        val typeA = Wire(new MxTypeBundle)
         typeA.exp := Mux(activation_mx_format === 2.U, 2.U,
                       Mux(activation_mx_format === 1.U, 3.U, 4.U))
         typeA.sig := Mux(activation_mx_format === 2.U, 2.U,
                       Mux(activation_mx_format === 1.U, 3.U, 4.U))
 
-        val typeW = Wire(new MxTypes)
+        val typeW = Wire(new MxTypeBundle)
         typeW.exp := Mux(weight_mx_format === 2.U, 2.U,
                       Mux(weight_mx_format === 1.U, 3.U, 4.U))
         typeW.sig := Mux(weight_mx_format === 2.U, 2.U,

src/main/scala/gemmini/Arithmetic.scala

@@ -4,6 +4,7 @@ package gemmini
 import chisel3._
 import chisel3.util._
 import chisel3.experimental._
+import mxgen.{MxTypeBundle, requiredPEMode}
 
 /**
   * A Grid is a 2D array of Tile modules with registers in between each tile and
@@ -69,15 +70,15 @@ class Mesh[T <: Data : Arithmetic](inputType: T, weightType: T, outputType: T, a
   //   tile.io.weight_mx_format := io.weight_mx_format
   // }
 
-  val typeA = Wire(new MxTypes)
+  val typeA = Wire(new MxTypeBundle)
   typeA.exp := Mux(io.activation_mx_format === 2.U, 2.U,
                 Mux(io.activation_mx_format === 1.U, 3.U, 4.U))
   typeA.sig := Mux(io.activation_mx_format === 2.U, 2.U,
                 Mux(io.activation_mx_format === 1.U, 3.U, 4.U))
   val typeA_size = Mux(io.activation_mx_format === 2.U, 4.U,
                 Mux(io.activation_mx_format === 1.U, 6.U, 8.U))
 
-  val typeW = Wire(new MxTypes)
+  val typeW = Wire(new MxTypeBundle)
   typeW.exp := Mux(io.weight_mx_format === 2.U, 2.U,
                 Mux(io.weight_mx_format === 1.U, 3.U, 4.U))
   typeW.sig := Mux(io.weight_mx_format === 2.U, 2.U,