Fix comparison with different signedness

Author: tyfkda

src/cc/arch/aarch64/ir_aarch64.c

@@ -703,8 +703,7 @@ static void ei_cast(IR *ir) {
     }
   } else {
     // fix->fix
-    assert(ir->dst->vsize != ir->opr1->vsize);
-    if (ir->dst->vsize < ir->opr1->vsize) {
+    if (ir->dst->vsize <= ir->opr1->vsize) {
       if (ir->dst->phys != ir->opr1->phys) {
         int pow = ir->dst->vsize;
         assert(0 <= pow && pow < 4);

src/cc/arch/riscv64/ir_riscv64.c

@@ -620,28 +620,30 @@ static void ei_cast(IR *ir) {
     }
   } else {
     // fix->fix
-    assert(ir->dst->vsize != ir->opr1->vsize);
     int pows = ir->opr1->vsize;
     int powd = ir->dst->vsize;
     assert(0 <= pows && pows < 4);
     assert(0 <= powd && powd < 4);
     int pow = MIN(powd, pows);
     const char *dst = kReg64s[ir->dst->phys], *src = kReg64s[ir->opr1->phys];
-
-    if (ir->flag & IRF_UNSIGNED) {
-      switch (pow) {
-      case 0:  ZEXT_B(dst, src); break;
-      case 1:  ZEXT_H(dst, src); break;
-      case 2:  ZEXT_W(dst, src); break;
-      default: assert(false); break;
-      }
-    } else {
-      switch (pow) {
-      case 0:  SEXT_B(dst, src); break;
-      case 1:  SEXT_H(dst, src); break;
-      case 2:  SEXT_W(dst, src); break;
-      default: assert(false); break;
+    if (pow < 3) {
+      if (((ir->flag & IRF_UNSIGNED) != 0) == (powd > pows)) {
+        switch (pow) {
+        case 0:  ZEXT_B(dst, src); break;
+        case 1:  ZEXT_H(dst, src); break;
+        case 2:  ZEXT_W(dst, src); break;
+        default: assert(false); break;
+        }
+      } else {
+        switch (pow) {
+        case 0:  SEXT_B(dst, src); break;
+        case 1:  SEXT_H(dst, src); break;
+        case 2:  SEXT_W(dst, src); break;
+        default: assert(false); break;
+        }
       }
+    } else if (ir->dst->phys != ir->opr1->phys) {
+      MV(dst, src);
     }
   }
 }

src/cc/arch/x64/ir_x64.c

@@ -727,8 +727,7 @@ static void ei_cast(IR *ir) {
     }
   } else {
     // fix->fix
-    assert(ir->dst->vsize != ir->opr1->vsize);
-    if (ir->dst->vsize < ir->opr1->vsize) {
+    if (ir->dst->vsize <= ir->opr1->vsize) {
       if (ir->dst->phys != ir->opr1->phys) {
         int pow = ir->dst->vsize;
         assert(0 <= pow && pow < 4);

src/cc/backend/codegen_expr.c

@@ -206,7 +206,8 @@ static VReg *gen_cast(Expr *expr) {
 
   size_t src_size = 1U << vreg->vsize;
   if (dst_size == src_size &&
-      is_flonum(dst_type) == ((vreg->flag & VRF_FLONUM) != 0))
+      is_flonum(dst_type) == ((vreg->flag & VRF_FLONUM) != 0) &&
+      (is_flonum(dst_type) || is_unsigned(dst_type) == is_unsigned(src->type)))
     return vreg;
 
   IR *ir = new_ir_cast(vreg, to_vsize(dst_type), to_vflag(dst_type));

tests/valtest.c

@@ -335,6 +335,11 @@ TEST(all) {
     EXPECT("compare with different sign1", 1, minus > uone);  // !!!
     EXPECT("compare with different sign2", 1, uone < minus);  // !!!
     EXPECT("compare with hex literal", 1, minus < 0xf6);  // Hex literal is signed.
+
+    int32_t x = -20;
+    uint32_t y = -10;
+    EXPECT_TRUE(y > x);
+    EXPECT("compare with different sign3", 111, y > x ? 111 : -111);
   }
   EXPECT("condition is true", true, (x = 3, (x != 0) == true));
   EXPECT("condition is not true", false, (x = 4, (x > 0) != true));