We should consider allowing implementations to enable/disable CHERI via xenvcfg.Y without needing to support hybrid mode, and so without allocating the P-bit in the metadata.
Currently you need to have both, but I think it's reasonable to be able to run standard RISC-V binaries without supporting hybrid mode.
This is a proposed re-organisation of extensions, not a spec change as such.
We should consider allowing implementations to enable/disable CHERI via xenvcfg.Y without needing to support hybrid mode, and so without allocating the P-bit in the metadata.
Currently you need to have both, but I think it's reasonable to be able to run standard RISC-V binaries without supporting hybrid mode.
This is a proposed re-organisation of extensions, not a spec change as such.