From b7e9a8358fe71ef9b32670bf9c734be90ab26efc Mon Sep 17 00:00:00 2001 From: Manuel Stahl Date: Tue, 16 Jun 2026 14:45:39 +0200 Subject: [PATCH] Update MPFS_Sysreg register values Reset values are taken from https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/SupportingCollateral/PolarFireSoC_Register_Map.zip --- .../Peripherals/Miscellaneous/MPFS_Sysreg.cs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/Emulator/Peripherals/Peripherals/Miscellaneous/MPFS_Sysreg.cs b/src/Emulator/Peripherals/Peripherals/Miscellaneous/MPFS_Sysreg.cs index 4b96728ac..eb5ab3c9e 100644 --- a/src/Emulator/Peripherals/Peripherals/Miscellaneous/MPFS_Sysreg.cs +++ b/src/Emulator/Peripherals/Peripherals/Miscellaneous/MPFS_Sysreg.cs @@ -95,7 +95,7 @@ public MPFS_Sysreg(IMachine machine) }, // Holds the MSS peripherals in reset. When in reset the peripheral should not be accessed. - {(long)Registers.SoftResetCr, new DoubleWordRegister(this, 0x7FFFFFFE) + {(long)Registers.SoftResetCr, new DoubleWordRegister(this, 0x3FFFFFFE) .WithFlag(0, writeCallback: (_, val) => ManageSoftReset(val, 0), name: "ENVM") .WithFlag(1, writeCallback: (_, val) => ManageSoftReset(val, 1), name: "MAC0") .WithFlag(2, writeCallback: (_, val) => ManageSoftReset(val, 2), name: "MAC1") @@ -132,13 +132,13 @@ public MPFS_Sysreg(IMachine machine) {(long)Registers.ClockConfigCr, new DoubleWordRegister(this, 0x10) .WithTag("ClockConfig", 0, 32) }, - {(long)Registers.EnvmCr, new DoubleWordRegister(this, 0xFF) + {(long)Registers.EnvmCr, new DoubleWordRegister(this, 0x4005004F) .WithTag("Envm", 0, 32) }, - {(long)Registers.RtcClockCr, new DoubleWordRegister(this, 0x1064) + {(long)Registers.RtcClockCr, new DoubleWordRegister(this, 0x10064) .WithTag("RtcClock", 0, 32) }, - {(long)Registers.PllStatusSr, new DoubleWordRegister(this, 0x707) + {(long)Registers.PllStatusSr, new DoubleWordRegister(this, 0x0) .WithTag("PllStatus", 0, 32) }, {(long)Registers.EdacSr, new DoubleWordRegister(this) @@ -384,4 +384,4 @@ private enum Registers SparePerimRw = 0x2DC } } -} \ No newline at end of file +}