imm_generator.v

module imm_generator (
    input  wire [31:0] instr,
    output reg  [31:0] imm_out
);

    wire [6:0] opcode = instr[6:0];

    always @(*) begin
        case (opcode)
        //I-type
            7'b0010011, // arithemetic ones
            7'b0000011, // load
            7'b1100111: // jalr
                imm_out = {{20{instr[31]}}, instr[31:20]}; // Sign extension of 12 bits

            7'b0100011: // S-type
                imm_out = {{20{instr[31]}}, instr[31:25], instr[11:7]}; // Sign extension of 12 bits

            7'b1100011: // B-type
                imm_out = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; // Sign extension 13 bits
            //U-type
            7'b0010111, // AUIPC
            7'b0110111: // LUI
                imm_out = {instr[31:12], 12'b0};

            7'b1101111: // J-type
                imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; // Sign-extend 21 bits

            default:
                imm_out = 32'b0; 
        endcase
    end

endmodule