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verif: Add framework for benchmarking sweep across different hw configs
1 parent afa2bfc commit f60f0b4

15 files changed

Lines changed: 1948 additions & 24 deletions

‎.gitignore‎

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@@ -9,3 +9,4 @@ target/verif/vsim/compile.tcl
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target/verif/vsim/modelsim.ini
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target/verif/vsim/transcript
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target/verif/vsim/vsim.wlf
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target/verif/results

‎target/verif/config/generated/json_to_mk.py‎

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Templates are automatically discovered based on the config type argument.
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"""
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import json
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import argparse
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import json
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import sys
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from pathlib import Path
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from string import Template
@@ -83,9 +83,9 @@ def parse_args(argv=None):
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help="Configuration type to generate.",
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)
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parser.add_argument(
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"config_dir",
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"config_json",
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type=Path,
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help="Directory containing source-of-truth JSON files.",
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help="Path to selected source-of-truth JSON file.",
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)
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parser.add_argument(
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"generated_dir",
@@ -98,11 +98,10 @@ def parse_args(argv=None):
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def main():
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args = parse_args()
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config_type = args.config_type
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config_dir = args.config_dir.resolve()
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json_file = args.config_json.resolve()
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config_dir = json_file.parent
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generated_dir = args.generated_dir.resolve()
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# Construct file paths based on config_type argument
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json_file = config_dir / f"{config_type}.json"
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template_file = generated_dir / f"{config_type}.mk.tpl"
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# Load JSON config

‎target/verif/config/hardware.json‎

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"DATA_WIDTH": 32,
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"TOT_MEM_SIZE": 256,
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"N_BANKS": 64,
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"INTERCO_TYPE": "MUX",
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"INTERCO_TYPE": "HCI",
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"TS_BIT": 21,
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"EXPFIFO": 0,
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"SEL_LIC": 0

‎target/verif/config/sweep_hardware/hardware_hci_2hwpe_8fact.json‎

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{
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"description": "Hardware configuration parameters for HCI interconnect",
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"parameters": {
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"N_HWPE": 2,
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"HWPE_WIDTH_FACT": 8,
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"N_CORE": 8,
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"N_DMA": 0,
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"N_EXT": 1,
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"DATA_WIDTH": 32,
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"TOT_MEM_SIZE": 256,
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"N_BANKS": 64,
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"INTERCO_TYPE": "HCI",
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"TS_BIT": 21,
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"EXPFIFO": 0,
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"SEL_LIC": 0
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}
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}

‎target/verif/config/sweep_hardware/hardware_log_2hwpe_8fact.json‎

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{
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"description": "Hardware configuration parameters for HCI interconnect",
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"parameters": {
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"N_HWPE": 2,
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"HWPE_WIDTH_FACT": 8,
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"N_CORE": 8,
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"N_DMA": 0,
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"N_EXT": 1,
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"DATA_WIDTH": 32,
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"TOT_MEM_SIZE": 256,
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"N_BANKS": 64,
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"INTERCO_TYPE": "LOG",
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"TS_BIT": 21,
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"EXPFIFO": 0,
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"SEL_LIC": 0
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}
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}

‎target/verif/config/sweep_hardware/hardware_mux_2hwpe_8fact.json‎

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{
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"description": "Hardware configuration parameters for HCI interconnect",
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"parameters": {
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"N_HWPE": 2,
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"HWPE_WIDTH_FACT": 8,
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"N_CORE": 8,
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"N_DMA": 0,
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"N_EXT": 1,
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"DATA_WIDTH": 32,
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"TOT_MEM_SIZE": 256,
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"N_BANKS": 64,
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"INTERCO_TYPE": "MUX",
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"TS_BIT": 21,
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"EXPFIFO": 0,
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"SEL_LIC": 0
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}
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}

‎target/verif/config/workload.json‎

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"hwpe_masters": [
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{
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"id": 1,
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"id": 0,
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"description": "DMA engine (linear setup + ping/pong prefetch)",
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"patterns": [
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{
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]
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},
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{
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"id": 0,
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"id": 1,
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"description": "Single GEMM engine processing 4 tiles with ping/pong buffers",
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"patterns": [
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{

‎target/verif/config/workloads/workload_dma_gemm.json‎

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{
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"description": "Simple 4-tile double-buffer GEMM. DMA uses linear transfers sized only by region_size_bytes.",
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"log_masters": [
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{ "id": 0, "description": "Core 0 (idle)", "mem_access_type": "idle" },
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{ "id": 1, "description": "Core 1 (idle)", "mem_access_type": "idle" },
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{ "id": 2, "description": "Core 2 (idle)", "mem_access_type": "idle" },
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{ "id": 3, "description": "Core 3 (idle)", "mem_access_type": "idle" },
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{ "id": 4, "description": "Core 4 (idle)", "mem_access_type": "idle" },
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{ "id": 5, "description": "Core 5 (idle)", "mem_access_type": "idle" },
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{ "id": 6, "description": "Core 6 (idle)", "mem_access_type": "idle" },
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{ "id": 7, "description": "Core 7 (idle)", "mem_access_type": "idle" },
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{ "id": 8, "description": "External 0 (idle)", "mem_access_type": "idle" }
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],
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"hwpe_masters": [
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{
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"id": 0,
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"description": "DMA engine (linear setup + ping/pong prefetch)",
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"patterns": [
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{
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"description": "Setup preload: B matrix (8 KiB)",
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"mem_access_type": "linear",
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"job": "dma_load_B",
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"traffic_pct": 100,
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"traffic_read_pct": 0,
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"region_base_address": "0x00000",
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"region_size_bytes": 8192
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},
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{
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"description": "Setup preload: tile A0 into buffer #0 (8 KiB)",
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"mem_access_type": "linear",
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"job": "dma_load_A0_buf0",
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"traffic_pct": 100,
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"traffic_read_pct": 0,
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"region_base_address": "0x02000",
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"region_size_bytes": 8192
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},
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{
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"description": "Setup preload: tile A1 into buffer #1 (8 KiB)",
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"mem_access_type": "linear",
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"job": "dma_load_A1_buf1",
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"traffic_pct": 100,
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"traffic_read_pct": 0,
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"region_base_address": "0x04000",
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"region_size_bytes": 8192
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},
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{
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"description": "Prefetch tile A2 into buffer #0 (8 KiB)",
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"mem_access_type": "linear",
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"job": "dma_load_A2_buf0",
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"wait_for_jobs": ["gemm_A0"],
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"traffic_pct": 100,
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"traffic_read_pct": 0,
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"region_base_address": "0x02000",
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"region_size_bytes": 8192
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},
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{
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"description": "Read back C0 after GEMM tile A0",
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"mem_access_type": "linear",
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"job": "dma_store_C0_buf2",
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"wait_for_jobs": ["gemm_A0"],
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"traffic_pct": 100,
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"traffic_read_pct": 100,
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"region_base_address": "0x06000",
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"region_size_bytes": 8192
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},
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{
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"description": "Prefetch tile A3 into buffer #1 (8 KiB)",
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"mem_access_type": "linear",
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"job": "dma_load_A3_buf1",
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"wait_for_jobs": ["gemm_A1"],
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"traffic_pct": 100,
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"traffic_read_pct": 0,
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"region_base_address": "0x04000",
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"region_size_bytes": 8192
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},
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{
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"description": "Read back C1 after GEMM tile A1",
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"mem_access_type": "linear",
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"job": "dma_store_C1_buf3",
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"wait_for_jobs": ["gemm_A1"],
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"traffic_pct": 100,
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"traffic_read_pct": 100,
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"region_base_address": "0x08000",
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"region_size_bytes": 8192
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},
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{
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"description": "Read back C0 after GEMM tile A2",
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"mem_access_type": "linear",
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"job": "dma_store_C2_buf2",
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"wait_for_jobs": ["gemm_A2"],
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"traffic_pct": 100,
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"traffic_read_pct": 100,
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"region_base_address": "0x06000",
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"region_size_bytes": 8192
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},
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{
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"description": "Read back C1 after GEMM tile A3",
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"mem_access_type": "linear",
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"job": "dma_store_C3_buf3",
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"wait_for_jobs": ["gemm_A3"],
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"traffic_pct": 100,
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"traffic_read_pct": 100,
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"region_base_address": "0x08000",
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"region_size_bytes": 8192
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}
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]
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},
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{
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"id": 1,
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"description": "Single GEMM engine processing 4 tiles with ping/pong buffers",
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"patterns": [
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{
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"description": "GEMM tile A0: A0 x B -> C0",
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"mem_access_type": "matmul_phased",
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"job": "gemm_A0",
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"wait_for_jobs": ["dma_load_B", "dma_load_A0_buf0"],
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"traffic_pct": 90,
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"matrix_m": 16,
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"matrix_n": 16,
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"matrix_k": 16,
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"region_base_address_a": "0x02000",
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"region_size_bytes_a": 8192,
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"region_base_address_b": "0x00000",
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"region_size_bytes_b": 8192,
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"region_base_address_c": "0x06000",
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"region_size_bytes_c": 8192
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},
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{
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"description": "GEMM tile A1: A1 x B -> C1",
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"mem_access_type": "matmul_phased",
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"job": "gemm_A1",
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"wait_for_jobs": ["dma_load_B", "dma_load_A1_buf1"],
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"traffic_pct": 90,
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"matrix_m": 16,
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"matrix_n": 16,
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"matrix_k": 16,
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"region_base_address_a": "0x04000",
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"region_size_bytes_a": 8192,
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"region_base_address_b": "0x00000",
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"region_size_bytes_b": 8192,
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"region_base_address_c": "0x08000",
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"region_size_bytes_c": 8192
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},
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{
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"description": "GEMM tile A2: A0 x B -> C0 (after dma_load_A2_buf0)",
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"mem_access_type": "matmul_phased",
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"job": "gemm_A2",
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"wait_for_jobs": ["dma_load_B", "dma_load_A2_buf0", "dma_store_C0_buf2"],
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"traffic_pct": 90,
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"matrix_m": 16,
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"matrix_n": 16,
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"matrix_k": 16,
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"region_base_address_a": "0x02000",
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"region_size_bytes_a": 8192,
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"region_base_address_b": "0x00000",
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"region_size_bytes_b": 8192,
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"region_base_address_c": "0x06000",
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"region_size_bytes_c": 8192
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},
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{
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"description": "GEMM tile A3: A1 x B -> C1 (after dma_load_A3_buf1)",
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"mem_access_type": "matmul_phased",
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"job": "gemm_A3",
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"wait_for_jobs": ["dma_load_B", "dma_load_A3_buf1", "dma_store_C1_buf3"],
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"traffic_pct": 90,
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"matrix_m": 16,
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"matrix_n": 16,
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"matrix_k": 16,
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"region_base_address_a": "0x04000",
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"region_size_bytes_a": 8192,
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"region_base_address_b": "0x00000",
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"region_size_bytes_b": 8192,
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"region_base_address_c": "0x08000",
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"region_size_bytes_c": 8192
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}
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]
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}
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]
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}

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