Convert "hci-outstanding" modules back to "hci-core" modules

Author: mbertuletti

Bender.yml

@@ -43,17 +43,15 @@ sources:
       - rtl/core/hci_core_mux_ooo.sv
       - rtl/core/hci_core_r_valid_filter.sv
       - rtl/core/hci_core_r_id_filter.sv
+      - rtl/core/hci_core_rob.sv
       - rtl/core/hci_core_source.sv
       - rtl/core/hci_core_source_v2.sv
       - rtl/core/hci_core_split.sv
       - rtl/ecc/hci_ecc_dec.sv
       - rtl/ecc/hci_ecc_enc.sv
       - rtl/ecc/hci_ecc_manager.sv
-      - rtl/outstanding/hci_outstanding_assign.sv
-      - rtl/outstanding/hci_outstanding_mux.sv
-      - rtl/outstanding/hci_outstanding_rob.sv
-      - rtl/outstanding/hci_outstanding_source.sv
-      - rtl/outstanding/hci_outstanding_fifo.sv
+      - rtl/variablelatency/hci_variablelatency_assign.sv
+      - rtl/variablelatency/hci_variablelatency_tocore.sv
       - rtl/interco/hci_log_interconnect.sv
       - rtl/interco/deprecated/hci_log_interconnect_l2.sv
       - rtl/interco/hci_new_log_interconnect.sv # `new_XBAR_TCDM` dep. is a private repo
@@ -66,7 +64,6 @@ sources:
       - rtl/core/hci_core_sink.sv
       - rtl/ecc/hci_ecc_source.sv
       - rtl/core/hci_core_sink_v2.sv
-      - rtl/outstanding/hci_outstanding_sink.sv
       - rtl/interco/hci_router.sv
       # Level 4
       - rtl/ecc/hci_ecc_interconnect.sv

rtl/common/hci_helpers.svh

@@ -346,15 +346,15 @@
   `define HCI_SIZE_CHECK_ASSERTS(__intf) `HCI_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(__intf), __intf)
 
   // Asserts (generic definition usable with any parameter name)
-  `define HCI_OUTSTANDING_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(__xparam, __xintf) \
+  `define HCI_VARIABLELATENCY_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(__xparam, __xintf) \
   initial __xparam``_intf_size_check_dw  : assert(__xparam.DW  == `HCI_SIZE_GET_DW_CHECK(__xintf)); \
   initial __xparam``_intf_size_check_bw  : assert(__xparam.BW  == `HCI_SIZE_GET_BW_CHECK(__xintf)); \
   initial __xparam``_intf_size_check_aw  : assert(__xparam.AW  == `HCI_SIZE_GET_AW_CHECK(__xintf)); \
   initial __xparam``_intf_size_check_uw  : assert(__xparam.UW  == `HCI_SIZE_GET_UW_CHECK(__xintf)); \
   initial __xparam``_intf_size_check_iw  : assert(__xparam.IW  == `HCI_SIZE_GET_IW_CHECK(__xintf));
 
   // Asserts (specialized definition for conventional param names
-  `define HCI_OUTSTANDING_SIZE_CHECK_ASSERTS(__intf) `HCI_OUTSTANDING_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(__intf), __intf)
+  `define HCI_VARIABLELATENCY_SIZE_CHECK_ASSERTS(__intf) `HCI_VARIABLELATENCY_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(__intf), __intf)
 
 `endif
 

rtl/common/hci_interfaces.sv

@@ -208,7 +208,7 @@ interface hci_core_intf (
 
 endinterface // hci_core_intf
 
-interface hci_outstanding_intf (
+interface hci_variablelatency_intf (
   input logic clk
 );
 
@@ -291,7 +291,7 @@ interface hci_outstanding_intf (
     input resp_ready
   );
 
-endinterface // hci_outstanding_intf
+endinterface // hci_variablelatency_intf
 
 `ifdef BUILD_DEPRECATED
 interface hci_mem_intf (

rtl/outstanding/hci_outstanding_rob.sv rtl/core/hci_core_rob.svrtl/outstanding/hci_outstanding_rob.sv renamed to rtl/core/hci_core_rob.sv

@@ -1,5 +1,5 @@
 /*
- * hci_outstanding_rob.sv
+ * hci_core_rob.sv
  * Marco Bertuletti <mbertuletti@iis.ee.ethz.ch>
  *
  * Copyright (C) 2017-2023 ETH Zurich, University of Bologna
@@ -14,16 +14,16 @@
  */
 
 /**
- * The **HCI-Outstanding reorder buffer** issues requests with up to ROB_NW
+ * The **HCI-Core reorder buffer** issues requests with up to ROB_NW
  * unique user-IDs. The responses can be retired out-of-order, by comparing
  * the incoming response user-ID with the issued IDs. As the user-ID is
  * implemented as user signal, any module coming after (i.e., nearer to memory
  * side) with respect to this block must respect user signals - specifically
  * it must return them identical in the response.
  *
  * .. tabularcolumns:: |l|l|J|
- * .. _hci_outstanding_rob_params:
- * .. table:: **hci_outstanding_mux** design-time parameters.
+ * .. _hci_core_rob_params:
+ * .. table:: **hci_core_rob** design-time parameters.
  *
  *   +------------+-------------+-----------------------------------------------+
  *   | **Name**   | **Default** | **Description**                               |
@@ -35,7 +35,7 @@
 
 `include "hci_helpers.svh"
 
-module hci_outstanding_rob
+module hci_core_rob
   import hwpe_stream_package::*;
   import hci_package::*;
   import cf_math_pkg::idx_width;
@@ -48,15 +48,17 @@ module hci_outstanding_rob
   input  logic  clk_i,
   input  logic  rst_ni,
 
-  hci_outstanding_intf.target    in,
-  hci_outstanding_intf.initiator out
+  hci_core_intf.target    in,
+  hci_core_intf.initiator out
 );
 
   localparam int unsigned DW  = `HCI_SIZE_GET_DW(out);
   localparam int unsigned BW  = `HCI_SIZE_GET_BW(out);
   localparam int unsigned AW  = `HCI_SIZE_GET_AW(out);
   localparam int unsigned UW  = `HCI_SIZE_GET_UW(out);
   localparam int unsigned IW  = `HCI_SIZE_GET_IW(out);
+  localparam int unsigned EW  = `HCI_SIZE_GET_EW(out);
+  localparam int unsigned EHW = `HCI_SIZE_GET_EHW(out);
 
   // Pointers to memory queue and total words counter
   logic [ROB_IW-1:0] read_pointer_p, read_pointer_q;
@@ -72,39 +74,55 @@ module hci_outstanding_rob
   // Memory queue
   logic [ROB_NW-1:0][IW-1:0] mem_req_id_p, mem_req_id_q;
   logic [ROB_NW-1:0][DW-1:0] mem_resp_data_p, mem_resp_data_q;
+  logic [ROB_NW-1:0][EW-1:0] mem_resp_ecc_p, mem_resp_ecc_q;
   logic [ROB_NW-1:0] mem_resp_opc_p, mem_resp_opc_q;
   logic [ROB_NW-1:0] mem_resp_valid_p, mem_resp_valid_q;
 
   // HCI Port Left assignment
-  assign out.req_add     = in.req_add;
-  assign out.req_wen     = in.req_wen;
-  assign out.req_be      = in.req_be;
-  assign out.req_data    = in.req_data;
+  assign out.add     = in.add;
+  assign out.wen     = in.wen;
+  assign out.be      = in.be;
+  assign out.data    = in.data;
+  assign out.ecc     = in.ecc;
 
   // Assign unique ROB ID to the user field
-  assign out.req_user    = write_pointer_q;
-  assign out.req_id      = in.req_id;
-  assign out.req_valid   = !full & in.req_valid;
-  assign in.req_ready    = !full & out.req_ready;
+  assign out.user    = write_pointer_q;
+  assign out.id      = in.id;
+  assign out.req     = !full & in.req;
+  assign in.gnt      = !full & out.gnt;
 
   // HCI Port Right assignment
-  assign in.resp_data    = mem_resp_data_q[read_pointer_q];
-  assign in.resp_opc     = mem_resp_opc_q[read_pointer_q];
-  assign in.resp_user    = '0;
+  assign in.r_data    = mem_resp_data_q[read_pointer_q];
+  assign in.r_opc     = mem_resp_opc_q[read_pointer_q];
+  assign in.r_user    = '0;
+  assign in.r_ecc     = mem_resp_ecc_q[read_pointer_q];
 
   // ROB ID of the incoming response
-  assign in.resp_id      = mem_req_id_q[read_pointer_q];
-  assign in.resp_valid   = mem_resp_valid_q[read_pointer_q];
-  assign out.resp_ready  = !empty;
+  assign in.r_id      = mem_req_id_q[read_pointer_q];
+  assign in.r_valid   = mem_resp_valid_q[read_pointer_q];
+  assign out.r_ready  = !empty;
+
+  if (EHW > 0) begin : ecc_handshake_gen
+    assign out.ereq     = '{default: {out.req}};
+    assign in.egnt      = '{default: {in.gnt}};
+    assign in.r_evalid  = '{default: {in.r_valid}};
+    assign out.r_eready = '{default: {out.r_ready}};
+  end
+  else begin : no_ecc_handshake_gen
+    assign out.ereq     = '0;
+    assign in.egnt      = '1;
+    assign in.r_evalid  = '0;
+    assign out.r_eready = '1;
+  end
 
   // Assign status flags
   assign full  = (status_cnt_q == ROB_NW-1);
   assign empty = (status_cnt_q == 'd0);
 
   // Assign buffer commands
-  assign request_id = in.req_valid & in.req_ready;
-  assign pop 		    = mem_resp_valid_q[read_pointer_q] & in.resp_ready;
-  assign push 		  = out.resp_valid & out.resp_ready;
+  assign request_id = in.req & in.gnt;
+  assign pop 		    = mem_resp_valid_q[read_pointer_q] & in.r_ready;
+  assign push 		  = out.r_valid & out.r_ready;
 
   // Read and Write logic
   always_comb begin: read_write_comb
@@ -117,13 +135,14 @@ module hci_outstanding_rob
     // Maintain response queue & initiator_id queue
     mem_req_id_p     = mem_req_id_q;
     mem_resp_data_p  = mem_resp_data_q;
+    mem_resp_ecc_p   = mem_resp_ecc_q;
     mem_resp_opc_p   = mem_resp_opc_q;
     mem_resp_valid_p = mem_resp_valid_q;
 
     // Request an ID.
     if (request_id) begin
       // Store in the initiator_id queue
-      mem_req_id_p[write_pointer_q] = in.req_id;
+      mem_req_id_p[write_pointer_q] = in.id;
 
       // Increment the write pointer
       if (write_pointer_q == ROB_NW-1) begin
@@ -139,16 +158,18 @@ module hci_outstanding_rob
 
     // Push data
     if (push) begin
-      resp_write_id = out.resp_user;
-      mem_resp_data_p  [resp_write_id] = out.resp_data;
-      mem_resp_opc_p   [resp_write_id] = out.resp_opc;
-      mem_resp_valid_p [resp_write_id] = out.resp_valid;
+      resp_write_id = out.r_user;
+      mem_resp_data_p  [resp_write_id] = out.r_data;
+      mem_resp_ecc_p   [resp_write_id] = out.r_ecc;
+      mem_resp_opc_p   [resp_write_id] = out.r_opc;
+      mem_resp_valid_p [resp_write_id] = out.r_valid;
     end
 
     // Pop data
     if (pop) begin
       // Word was consumed
       mem_req_id_p[read_pointer_q] = 1'b0;
+      mem_resp_ecc_p[read_pointer_q] = '0;
       mem_resp_valid_p[read_pointer_q] = 1'b0;
 
       // Increment the read pointer
@@ -178,6 +199,7 @@ module hci_outstanding_rob
       // Memory queues
 	    mem_req_id_q     <= '0;
 	    mem_resp_data_q  <= '0;
+	    mem_resp_ecc_q   <= '0;
 	    mem_resp_opc_q   <= '0;
 	    mem_resp_valid_q <= '0;
     end
@@ -188,6 +210,7 @@ module hci_outstanding_rob
       // Memory queues
 	    mem_req_id_q     <= mem_req_id_p;
 	    mem_resp_data_q  <= mem_resp_data_p;
+	    mem_resp_ecc_q   <= mem_resp_ecc_p;
 	    mem_resp_opc_q   <= mem_resp_opc_p;
 	    mem_resp_valid_q <= mem_resp_valid_p;
     end
@@ -216,10 +239,10 @@ module hci_outstanding_rob
   initial
     iw_out :  assert(out.UW  >= $clog2(ROB_NW));
 
-  `HCI_OUTSTANDING_SIZE_CHECK_ASSERTS(out);
+  `HCI_VARIABLELATENCY_SIZE_CHECK_ASSERTS(out);
 
 `endif
 `endif
 `endif;
 
-endmodule: hci_outstanding_rob
+endmodule: hci_core_rob

rtl/core/hci_core_source.sv

@@ -223,7 +223,7 @@ module hci_core_source
     );
     assign addr_misaligned_push.data  = {6'b0, addr_pop.data[1:0]};
     assign addr_misaligned_push.strb  = '1;
-    assign addr_misaligned_push.valid = enable_i & tcdm.req & tcdm.gnt; // BEWARE: considered always ready!!!
+    assign addr_misaligned_push.valid = enable_i & tcdm.gnt; // BEWARE: considered always ready!!!
     assign addr_misaligned_pop.ready  = (tcdm.r_valid | stream_valid_q) & stream.ready;
     assign addr_misaligned_q = addr_misaligned_pop.data[1:0];
 
@@ -245,7 +245,7 @@ module hci_core_source
   end
 
   assign tcdm.r_ready = stream.ready;
-  assign tcdm.req     = (cs != STREAMER_IDLE) ? addr_pop.valid & stream.ready : '0;
+  assign tcdm.req     = (cs != STREAMER_IDLE) ? addr_pop.valid : '0;
   assign tcdm.add     = (cs != STREAMER_IDLE) ? {addr_pop.data[31:2],2'b0}    : '0;
   assign tcdm.wen     = 1'b1;
   assign tcdm.be      = 4'h0;
@@ -256,7 +256,7 @@ module hci_core_source
   assign stream.strb  = '1;
   assign stream.data  = stream_data_aligned;
   assign stream.valid = enable_i & (tcdm.r_valid | stream_valid_q); // is this strictly necessary to keep the HWPE-Stream protocol? or can be avoided with a FIFO q?
-  assign addr_pop.ready = (cs != STREAMER_IDLE) ? addr_pop.valid & stream.ready & tcdm.gnt : 1'b0;
+  assign addr_pop.ready = (cs != STREAMER_IDLE) ? tcdm.gnt : 1'b0;
 
   always_ff @(posedge clk_i or negedge rst_ni)
   begin