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🧬 Parameterize hci_router and hci_router_reorder for bank width
1 parent 87810a6 commit 29f91d5

2 files changed

Lines changed: 53 additions & 41 deletions

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‎rtl/interco/hci_router.sv‎

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,8 @@ module hci_router
9797
localparam int unsigned ELEM_ADDR_OFFSET = NUM_ELEM_WORD == 1 ? 0 : $clog2(NUM_ELEM_WORD);
9898
localparam int unsigned LSB_COMMON_ADDR = $clog2(NB_OUT_CHAN) + ELEM_ADDR_OFFSET;
9999
localparam int unsigned AWC = AWM+$clog2(NB_OUT_CHAN);
100+
// ECC width per bank word
101+
localparam int unsigned EW_BANK = $clog2(BANK_WORD_WIDTH)+2;
100102

101103
logic [$clog2(NB_OUT_CHAN)-1:0] bank_offset_s;
102104
logic virt_in_0_handshake_d, virt_in_0_handshake_q;
@@ -121,7 +123,7 @@ module hci_router
121123
BW: BANK_ELEM_WIDTH,
122124
UW: 0,
123125
IW: 0,
124-
EW: 7*USE_ECC,
126+
EW: EW_BANK*USE_ECC,
125127
EHW: EHW
126128
};
127129
hci_core_intf #(
@@ -218,10 +220,10 @@ module hci_router
218220

219221
assign virt_in[ii].r_ready = postfifo.r_ready;
220222

221-
// ecc and r_ecc are each EW=7 bits wide
223+
// ecc and r_ecc are each EW_BANK = $clog2(BANK_WORD_WIDTH)+2 bits wide
222224
if(USE_ECC) begin : ecc_assignment
223-
assign virt_in[ii].ecc = postfifo.ecc[ii*7+6:ii*7];
224-
assign postfifo.r_ecc[ii*7+6:ii*7] = virt_in[ii].r_ecc;
225+
assign virt_in[ii].ecc = postfifo.ecc[ii*EW_BANK +: EW_BANK];
226+
assign postfifo.r_ecc[ii*EW_BANK +: EW_BANK] = virt_in[ii].r_ecc;
225227
end else
226228
assign virt_in[ii].ecc = postfifo.ecc;
227229

@@ -292,9 +294,11 @@ module hci_router
292294
//Re-order the interfaces such that the port requesting the lowest bits of data
293295
//are located at the correct bank offset
294296
hci_router_reorder #(
295-
.NB_IN_CHAN ( NB_IN_CHAN ),
296-
.NB_OUT_CHAN ( NB_OUT_CHAN ),
297-
.USE_ECC ( USE_ECC ),
297+
.NB_IN_CHAN ( NB_IN_CHAN ),
298+
.NB_OUT_CHAN ( NB_OUT_CHAN ),
299+
.BANK_WORD_WIDTH ( BANK_WORD_WIDTH ),
300+
.BANK_ELEM_WIDTH ( BANK_ELEM_WIDTH ),
301+
.USE_ECC ( USE_ECC ),
298302
.FILTER_WRITE_R_VALID(FILTER_WRITE_R_VALID)
299303
) i_reorder (
300304
.clk_i ( clk_i ),

‎rtl/interco/hci_router_reorder.sv‎

Lines changed: 42 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,9 @@
1616
/**
1717
* The **hci_router_reorder** module is the actual routing engine wrapped by
1818
* **hci_router** (see :ref:`hci_router`). It accepts up to `NB_IN_CHAN`
19-
* 32-bit `in` HCI-Core channels and distributes their requests across
20-
* `NB_OUT_CHAN` `out` channels (typically one per memory bank) according to
21-
* the external `order_i` index, with no arbitration: per cycle, each `in`
19+
* `BANK_WORD_WIDTH`-bit `in` HCI-Core channels and distributes their requests
20+
* across `NB_OUT_CHAN` `out` channels (typically one per memory bank) according
21+
* to the external `order_i` index, with no arbitration: per cycle, each `in`
2222
* channel is routed to a distinct `out` channel determined by
2323
* `(order_i + i) mod NB_OUT_CHAN`.
2424
*
@@ -29,8 +29,9 @@
2929
* are demultiplexed back to the originating `in` channel via instances of
3030
* `addr_dec_resp_mux` (one per `in` channel).
3131
*
32-
* When `USE_ECC` is set, the 7 Hsiao SEC-DED check bits of the `ecc`
33-
* side-channel are routed alongside the data; otherwise they are tied off.
32+
* When `USE_ECC` is set, the `$clog2(BANK_WORD_WIDTH)+2` Hsiao SEC-DED check
33+
* bits of the `ecc` side-channel are routed alongside the data; otherwise they
34+
* are tied off.
3435
*
3536
* .. tabularcolumns:: |l|l|J|
3637
* .. _hci_router_reorder_params:
@@ -39,13 +40,17 @@
3940
* +------------------------+-------------+------------------------------------------------------------------------------+
4041
* | **Name** | **Default** | **Description** |
4142
* +------------------------+-------------+------------------------------------------------------------------------------+
42-
* | *NB_IN_CHAN* | 2 | Number of input HCI-Core channels (typically `DWH/32`). |
43+
* | *NB_IN_CHAN* | 2 | Number of input HCI-Core channels (typically `DWH/BANK_WORD_WIDTH`). |
4344
* +------------------------+-------------+------------------------------------------------------------------------------+
4445
* | *NB_OUT_CHAN* | 2 | Number of output HCI-Core channels (one per memory bank). |
4546
* +------------------------+-------------+------------------------------------------------------------------------------+
47+
* | *BANK_WORD_WIDTH* | 32 | Bit-width of one bank word (data width of each `in`/`out` channel). |
48+
* +------------------------+-------------+------------------------------------------------------------------------------+
49+
* | *BANK_ELEM_WIDTH* | 8 | Bit-width of one element within a bank word (`be` strobe granularity). |
50+
* +------------------------+-------------+------------------------------------------------------------------------------+
4651
* | *FILTER_WRITE_R_VALID* | 0 | If 1, suppress the `r_valid` pulse for write transactions on the response. |
4752
* +------------------------+-------------+------------------------------------------------------------------------------+
48-
* | *USE_ECC* | 0 | If 1, propagate the 7-bit ECC check bits alongside data. |
53+
* | *USE_ECC* | 0 | If 1, propagate the ECC check bits alongside data. |
4954
* +------------------------+-------------+------------------------------------------------------------------------------+
5055
*
5156
*/
@@ -54,6 +59,8 @@ module hci_router_reorder
5459
#(
5560
parameter int unsigned NB_IN_CHAN = 2,
5661
parameter int unsigned NB_OUT_CHAN = 2,
62+
parameter int unsigned BANK_WORD_WIDTH = 32,
63+
parameter int unsigned BANK_ELEM_WIDTH = 8,
5764
parameter int unsigned FILTER_WRITE_R_VALID = 0,
5865
parameter bit USE_ECC = 0
5966
)
@@ -69,33 +76,34 @@ module hci_router_reorder
6976

7077
);
7178

72-
// Hsiao SEC-DED ECC needs $clog2(DW)+2 check bits
73-
// At this level only data are ECC-protected and with DW fixed at 32 that is 5+2 = 7
74-
// When USE_ECC == 1 those 7 bits are appended to the 32-bit data word
75-
localparam int unsigned EW = (USE_ECC) ? 7 : 1;
76-
localparam int unsigned RESP_DATA_WIDTH = (USE_ECC) ? (32+7) : 32;
77-
78-
logic [NB_IN_CHAN-1:0] in_req;
79-
logic [NB_IN_CHAN-1:0] in_req_q;
80-
logic [NB_IN_CHAN-1:0][31:0] in_add;
81-
logic [NB_IN_CHAN-1:0] in_wen;
82-
logic [NB_IN_CHAN-1:0][3:0] in_be;
83-
logic [NB_IN_CHAN-1:0][31:0] in_data;
84-
logic [NB_IN_CHAN-1:0][EW-1:0] in_ecc;
85-
logic [NB_IN_CHAN-1:0] in_gnt;
86-
logic [NB_IN_CHAN-1:0][31:0] in_r_data;
87-
logic [NB_IN_CHAN-1:0] in_r_valid;
88-
logic [NB_IN_CHAN-1:0][EW-1:0] in_r_ecc;
89-
logic [NB_OUT_CHAN-1:0] out_req;
90-
logic [NB_OUT_CHAN-1:0][31:0] out_add;
91-
logic [NB_OUT_CHAN-1:0] out_wen;
92-
logic [NB_OUT_CHAN-1:0][3:0] out_be;
93-
logic [NB_OUT_CHAN-1:0][31:0] out_data;
94-
logic [NB_OUT_CHAN-1:0][EW-1:0] out_ecc;
95-
logic [NB_OUT_CHAN-1:0] out_gnt;
96-
logic [NB_OUT_CHAN-1:0][31:0] out_r_data;
97-
logic [NB_OUT_CHAN-1:0][EW-1:0] out_r_ecc;
98-
logic [NB_IN_CHAN-1:0][NB_OUT_CHAN-1:0] ma_req;
79+
// Width of the HCI byte-enable field
80+
localparam int unsigned BE_WIDTH = BANK_WORD_WIDTH / BANK_ELEM_WIDTH;
81+
// Hsiao SEC-DED ECC needs $clog2(DW)+2 check bits.
82+
// When USE_ECC == 1 those bits are appended to the BANK_WORD_WIDTH-bit data word.
83+
localparam int unsigned EW = (USE_ECC) ? ($clog2(BANK_WORD_WIDTH)+2) : 1;
84+
localparam int unsigned RESP_DATA_WIDTH = (USE_ECC) ? (BANK_WORD_WIDTH+EW) : BANK_WORD_WIDTH;
85+
86+
logic [NB_IN_CHAN-1:0] in_req;
87+
logic [NB_IN_CHAN-1:0] in_req_q;
88+
logic [NB_IN_CHAN-1:0][31:0] in_add;
89+
logic [NB_IN_CHAN-1:0] in_wen;
90+
logic [NB_IN_CHAN-1:0][BE_WIDTH-1:0] in_be;
91+
logic [NB_IN_CHAN-1:0][BANK_WORD_WIDTH-1:0] in_data;
92+
logic [NB_IN_CHAN-1:0][EW-1:0] in_ecc;
93+
logic [NB_IN_CHAN-1:0] in_gnt;
94+
logic [NB_IN_CHAN-1:0][BANK_WORD_WIDTH-1:0] in_r_data;
95+
logic [NB_IN_CHAN-1:0] in_r_valid;
96+
logic [NB_IN_CHAN-1:0][EW-1:0] in_r_ecc;
97+
logic [NB_OUT_CHAN-1:0] out_req;
98+
logic [NB_OUT_CHAN-1:0][31:0] out_add;
99+
logic [NB_OUT_CHAN-1:0] out_wen;
100+
logic [NB_OUT_CHAN-1:0][BE_WIDTH-1:0] out_be;
101+
logic [NB_OUT_CHAN-1:0][BANK_WORD_WIDTH-1:0] out_data;
102+
logic [NB_OUT_CHAN-1:0][EW-1:0] out_ecc;
103+
logic [NB_OUT_CHAN-1:0] out_gnt;
104+
logic [NB_OUT_CHAN-1:0][BANK_WORD_WIDTH-1:0] out_r_data;
105+
logic [NB_OUT_CHAN-1:0][EW-1:0] out_r_ecc;
106+
logic [NB_IN_CHAN-1:0][NB_OUT_CHAN-1:0] ma_req;
99107

100108
logic [NB_IN_CHAN-1:0 ][RESP_DATA_WIDTH-1:0] resp_data_o;
101109
logic [NB_OUT_CHAN-1:0][RESP_DATA_WIDTH-1:0] resp_data_i;

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