chore: sim test coverage — add tests for bus edge cases and compute mode transitions

[Jah-yee]

context

We have 18 TS tests and 25 Python tests. Coverage is decent but some paths are untested:

• Bus layer: what happens when cap_J overflows? when li_J hits 0? when rectified_W exceeds charge rate?
• Compute layer: mode transition edges — what triggers sleep→idle, idle→tx, tx→rx? Do the current draws match MODE_CURRENTS exactly?
• Full sim: restart after flameout with residual bus charge — does the state machine handle it cleanly?

goal

Add tests (TS and/or Python, your call) for these edge cases. Don't aim for 100% coverage — focus on the paths most likely to break if someone changes a constant or threshold.

notes

Look at existing tests in packages/sim/tests/ and python/sim_mini/tests/ for the pattern. Both use assert-based testing, no mocks.

[Jah-yee]

Partially addressed by PR #30 (edge-case tests for flameout, fuel exhaustion, kill during warmup). Bus edge cases (cap overflow, li_J=0, rectified_W > charge rate) and compute mode transitions still untested. Keeping open — lower priority than PR #30 unblockers (#44–#48).

[Jah-yee]

Implemented in stacked PR #54 on top of #53.\n\nScope:\n- paired TS/Python tests for bus saturation, LiFePO4 discharge after output cap depletion, and empty-store clamp behavior\n- paired TS/Python tests for LoRa compute mode thresholds and current draws across sleep/idle/engine_attn/compose/tx/rx\n- no production behavior changes\n\nValidation:\n- pnpm build\n- pnpm sim:test\n- pnpm py:test\n- pnpm sim:compare\n- pnpm golden:check\n- pnpm vapore:build\n- pnpm format:check\n\nThis should close #36 after the #53 -> #54 stack lands.