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    330 repositories

    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •61•327•3•5•Updated Sep 5, 2026Sep 5, 2026

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •4•6•8•10•Updated Sep 5, 2026Sep 5, 2026

    • redmule

      Public
      GEMM and GEMM-Ops accelerator for PULP systems
      SystemVerilog
      •
      Other
      •28•117•3•3•Updated Sep 5, 2026Sep 5, 2026

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •17•17•1•3•Updated Sep 5, 2026Sep 5, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •1k•25•1•0•Updated Sep 5, 2026Sep 5, 2026

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •27•37•3•2•Updated Sep 4, 2026Sep 4, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      SystemVerilog
      •
      Apache License 2.0
      •9•24•26•1•Updated Sep 4, 2026Sep 4, 2026

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      riscvdebug
      riscvdebug
      SystemVerilog
      •
      Other
      •100•324•15•4•Updated Sep 4, 2026Sep 4, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •53•169•4•18•Updated Sep 4, 2026Sep 4, 2026

    • TeraNoC

      Public
      An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
      C
      •
      Apache License 2.0
      •10•39•0•2•Updated Sep 4, 2026Sep 4, 2026

    • magia-sdk

      Public
      C
      •
      Apache License 2.0
      •11•7•8•9•Updated Sep 4, 2026Sep 4, 2026

    • pulp-sdk

      Public
      C
      •
      Apache License 2.0
      •82•128•19•12•Updated Sep 4, 2026Sep 4, 2026

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •11•39•2•7•Updated Sep 3, 2026Sep 3, 2026

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •205•793•7•2•Updated Sep 3, 2026Sep 3, 2026

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •59•236•21•12•Updated Sep 3, 2026Sep 3, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •63•390•33•19•Updated Sep 3, 2026Sep 3, 2026

    • PeakRDL-rawheader

      Public
      Python
      •
      Apache License 2.0
      •2•3•0•0•Updated Sep 1, 2026Sep 1, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •171•23•0•10•Updated Sep 1, 2026Sep 1, 2026

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •15•23•3•9•Updated Sep 1, 2026Sep 1, 2026

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •15•42•0•1•Updated Sep 1, 2026Sep 1, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      pythongeneratorsystemverilog
      pythongeneratorsystemverilognocaxi
      SystemVerilog
      •
      Apache License 2.0
      •77•338•24•3•Updated Sep 1, 2026Sep 1, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •119•365•21•30•Updated Aug 31, 2026Aug 31, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •21•17•6•2•Updated Aug 31, 2026Aug 31, 2026

    • ManyRVData

      Public
      This is the repository for CachePool architecture for the ManyRVData project
      C
      •
      Apache License 2.0
      •7•3•14•5•Updated Aug 31, 2026Aug 31, 2026

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilog
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •134•271•3•7•Updated Aug 30, 2026Aug 30, 2026

    • AraXL

      Public
      A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
      C
      •
      Other
      •8•9•2•2•Updated Aug 30, 2026Aug 30, 2026

    • spatz_vpu

      Public
      Spatz vector processing unit
      C
      •
      Apache License 2.0
      •4•1•0•2•Updated Aug 29, 2026Aug 29, 2026

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •10•21•0•7•Updated Aug 28, 2026Aug 28, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •372•1.7k•53•22•Updated Aug 27, 2026Aug 27, 2026

    • opope

      Public
      High frequency pipelined outer product
      SystemVerilog
      •
      Other
      •0•5•0•0•Updated Aug 27, 2026Aug 27, 2026
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