sdkconfig.defaults

# =============================================================================
# wii-ra-adapter  —  ESP-IDF v5.1 / arduino-esp32 3.0.x  —  ESP32-S3-WROOM-1 N16R8
#
# STAGE 1 (this file): replicate the Arduino build config EXACTLY (data cache
# still 32KB/32B). Goal: prove the IDF build runs identical to v0.32.2-wsteal
# (60fps @ 13k, achievement unlocks). NO perf change expected here.
#
# STAGE 2: flip CONFIG_ESP32S3_DATA_CACHE -> 64KB + LINE_64B (the whole point —
# the ~42KB of memref values thrash a 32KB cache but fit a 64KB one).
#
# Values mirrored from arduino-esp32 3.0.7 sdkconfig (idf-release_v5.1).
# =============================================================================
CONFIG_IDF_TARGET="esp32s3"

# --- Flash: 8MB, QIO @ 80MHz. ---
# 2026-06-29: this S3-MINI module has only 8MB flash (boot log: "detected chip: gd",
# "Detected size(8192k)"). Building for 16MB made init_flash assert ("Detected size
# smaller than the size in the binary image header") -> boot loop. Partition table
# reworked to single-app (factory 3MB) + ffat ~4.9MB to fit 8MB.
# 80M lock: that module's flash chip does NOT support HPM (boot log: "High performance
# mode of this flash model hasn't been supported"), so 120M flash is physically
# impossible — IDF was silently downgrading FLASHFREQ to "80m" anyway. Since octal
# flash and octal PSRAM share the MSPI core clock, this also forces PSRAM down to 80M.
CONFIG_ESPTOOLPY_FLASHSIZE_8MB=y
CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
# 120M works on the BIG DEV BOARD (flash has HPM) — measured 2026-06-30 (df5 vs df4):
# eval −27% (bandwidth-bound, scales with clock), df_us p50 −22%, df/s p10 50→54, but
# NOT solid 60 (p90 convergence spikes remain). To switch to the big board @120M:
#   CONFIG_ESPTOOLPY_FLASHFREQ_120M=y + CONFIG_BOOTLOADER_FLASH_DC_AWARE=y (this block)
#   CONFIG_SPIRAM_SPEED_120M=y + CONFIG_IDF_EXPERIMENTAL_FEATURES=y (PSRAM block below)
# The EXPERIMENTAL_FEATURES gate is MANDATORY — without it SPIRAM_SPEED_120M is
# un-selectable and silently falls to 40M -> flash120/psram40 fails the MSPI
# power-of-2 static_assert. The S3-MINI's GD flash has no HPM -> 120M impossible there.

# --- PSRAM: N16R8 = Octal (OPI) 8MB @ 80MHz. ---
# 2026-06-28: 80M for the S3-MINI target. The AP gen3 (APS6408) chip itself rates
# >120M, but octal PSRAM shares the MSPI core clock with flash, and flash is capped
# at 80M on this module (no HPM) — so 120M PSRAM is not reachable here regardless.
# 80M octal DDR is still ~160 MB/s and needs no experimental gating.
CONFIG_SPIRAM=y
CONFIG_SPIRAM_MODE_OCT=y
CONFIG_SPIRAM_TYPE_AUTO=y
CONFIG_SPIRAM_SPEED_80M=y
CONFIG_SPIRAM_BOOT_INIT=y
CONFIG_SPIRAM_USE_MALLOC=y
# CRITICAL mem-balance — the .ino's SRAM/PSRAM tuning (and the mbedTLS handshake
# headroom) was built against these EXACT values. Do not change in stage 1.
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=4096
CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=0

# --- Caches — data cache 64KB/64B (the IDF-migration lever: the ~84KB of SMG memref
#     values thrash a 32KB cache; 64KB holds ~76%). INSTRUCTION cache 32KB/64B.
#     CLEAN A/B 2026-07-01 (wii.log 32KB vs wii2.log 16KB, same fw): 32KB was ~2.5% faster
#     on evl (p50 10683 vs 10954) + df_us + frame-loss (2.9% vs 3.3%), ALL same direction
#     -> a small REAL gain (partly scene-confounded, but consistent). Costs 16KB internal
#     SRAM: sram-free 60KB (32KB) vs 76KB (16KB) at game-load. USER CHOSE 32KB, accepting
#     the tighter SRAM (mbedTLS→PSRAM keeps the network stable at 60KB). To reclaim the
#     16KB headroom instead, drop to _16KB/_32B. ---
# --- 2026-07-02 (later): 32KB RE-ENABLED, funded by the L1 cache resize
#     (4096->2048 slots, +13KB .bss back — see main.cpp L1_SLOTS comment).
#     Rationale: HARDCORE-MODE frame fidelity — the measured 16KB cost was
#     +0.85ms/frame on the SMG bunny chase (df_us p50 14.1->15.0ms), which
#     turned into 17 vs 1 lost frames in the chase (0.51% vs 0.03%); every
#     lost frame stretches timed challenges (the bunny's 1-minute timer), so
#     emulator-equal timing wants the 32KB. Net SRAM vs the 16KB build:
#     -16 (icache) +13 (L1) = -3KB; heap floor ~38KB expected (WS still fits).
#     (The brief 16KB experiment lives in git history; its analysis is in
#     memory: project_phase_c_chain_descriptors / project_sram_reclaim_backlog.) ---
CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB=y
CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_64B=y
CONFIG_ESP32S3_DATA_CACHE_64KB=y
CONFIG_ESP32S3_DATA_CACHE_LINE_64B=y

# --- Partition table: single-app 3MB factory / ~4.9MB FATFS (8MB flash) ---
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"

# --- Arduino as component: autostart setup()/loop() ---
CONFIG_AUTOSTART_ARDUINO=y
CONFIG_ARDUINO_LOOP_STACK_SIZE=8192

# --- FreeRTOS 1000 Hz tick (Arduino millis()/delay() semantics) ---
CONFIG_FREERTOS_HZ=1000

# --- CPU 240 MHz ---
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y

# --- Console UART baud = 250000 to match the app's Serial.begin(250000), so the
#     IDF boot/ESP_LOG output and the Arduino app logs share one baud (one monitor
#     baud for everything; the ROM's first line stays 115200 — unavoidable). ---
CONFIG_ESP_CONSOLE_UART_BAUDRATE=250000

# --- Task watchdog: DON'T watch IDLE on CPU1 (matches Arduino, which only checks
#     CPU0). The loopTask runs on CPU1 and legitimately hogs it for >5s during the
#     full-SMG achievement parse (rc_client_copy_achievements: 32k conditions) and
#     for the ~30ms do_frame — starving IDLE1 is expected, not a fault. ---
CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=n

# --- Compiler: -Os to match Arduino in stage 1 (try -O2 as a later experiment) ---
CONFIG_COMPILER_OPTIMIZATION_SIZE=y

# --- TLS for HTTPClient (RetroAchievements server over HTTPS) ---
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y
# PSK ciphersuites — arduino-esp32's ssl_client.cpp (NetworkClientSecure, used by
# HTTPClient for HTTPS) compiles its ENTIRE implementation only when a PSK key-
# exchange is enabled; without these the SSL symbols are absent → link errors
# (undefined start_ssl_client/ssl_init/...). Matches the Arduino default config.
CONFIG_MBEDTLS_PSK_MODES=y
CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK=y
CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK=y

# --- TLS memory: dynamic record buffers (2026-06-22, SSBM award failure) ---
# With this OFF, every HTTPS connection statically reserves a 16 KB internal-RAM
# RX buffer (CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN) and holds it for the whole
# connection. Login/startsession run BEFORE the rcheevos game struct loads
# (sram-free ~50-63 KB) so they fit; but heavy games (SSBM: 339 achievements,
# +37 KB SRAM struct) drop sram-free to ~25 KB / largest-block ~21 KB. The next
# HTTPS call (ping, awardachievement) then can't get the 16 KB block, and the
# hardware-AES DMA alloc fails downstream -> "esp-aes: Failed to allocate memory"
# -> start_ssl_client connect -1 -> the unlock is never submitted. SMG's smaller
# core set never crossed that line, which is why this only bit on SSBM.
# DYNAMIC_BUFFER allocates the RX buffer per-record and frees it when idle, and
# right-sizes it (the award response is ~100 B), recovering ~16 KB contiguous
# internal RAM exactly where the handshake needs it.
CONFIG_MBEDTLS_DYNAMIC_BUFFER=y
CONFIG_MBEDTLS_DYNAMIC_FREE_PEER_CERT=y
CONFIG_MBEDTLS_DYNAMIC_FREE_CONFIG_DATA=y

# --- TLS memory: allocate mbedTLS buffers in PSRAM, not internal SRAM (2026-07-01). ---
# Default was INTERNAL_MEM_ALLOC -> the ~16KB TLS RX buffer + handshake structs ate
# internal SRAM, which starved the hardware-AES DMA alloc on low-headroom games (the
# SSBM failure above) AND floods "setSocketOption fail errno 9" + task_wdt when SRAM is
# tight. EXTERNAL routes mbedTLS to PSRAM: TLS is NOT speed-critical (one handshake at
# login), and the ESP32-S3 GDMA CAN reach PSRAM so hardware SHA/AES still work (IDF uses
# internal DMA bounce buffers where needed). Frees ~16-32KB internal SRAM -> fixes the
# handshake starvation AND pays for the 32KB I-cache above. Fallback if crypto-DMA
# complains: CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC (big buffers PSRAM, small stay internal).
# CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC is not set
CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=y

# WebSocket dashboard (ra_web): enable esp_http_server WS server support.
CONFIG_HTTPD_WS_SUPPORT=y

# ra_web dashboard — keep the web/mDNS/WiFi network stack off the scarce internal
# SRAM (rcheevos already leaves only ~18KB free). Without these, mDNS packet
# allocs + RA-server TLS pings fail (mdns_send OOM / start_ssl_client socket err).
CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y
CONFIG_MDNS_MEMORY_ALLOC_SPIRAM=y
CONFIG_MDNS_TASK_CREATE_FROM_SPIRAM=y