new_dynarec: native Apple Silicon (darwin-arm64) support

Enable the arm64 new_dynarec on macOS, previously hard-disabled with
NO_ASM=1. Three independent blockers, three fixes:

1. linkage_arm64.S only assembled with ELF toolchains. Add a Mach-O
   variant of the symbol macros: leading-underscore C symbols,
   .private_extern instead of .hidden (.type/.size dropped, ELF-only),
   sym@PAGE/sym@PAGEOFF instead of :lo12: adrp relocations, and '%%'
   statement separators because the Darwin arm64 assembler treats ';'
   as a comment. Dot-prefixed local labels (ELF-only) become numbered
   locals. ELF output is unchanged (verified by cross-assembling for
   aarch64-linux before/after).

2. Apple Silicon enforces W^X. The code cache is now allocated with
   MAP_JIT at a dynamic address (static memory cannot be made
   executable on this platform), and every code path that writes to
   the cache is bracketed with pthread_jit_write_protect_np() via
   reentrant jit_write_begin/end helpers. The bracket points are the
   five C entry points all cache writes funnel through
   (new_recompile_block, dynamic_linker{,_ds}, invalidate_block,
   invalidate_all_pages) plus the arch_init trampoline setup; the
   assembly stubs need no changes because exec mode is the default.

3. cache_flush() reads ctr_el0, which traps (SIGILL) from EL0 on
   Apple Silicon. Use the system-provided sys_icache_invalidate()
   instead. This was the cause of the "continuous SIGILLs" reported
   when compiling the dynarec on M-series machines.

Tested on an M-series Mac (macOS 26.5): two commercial ROMs run on
the dynarec under the stock mupen64plus 2.6.0 frontend/plugins, with
generated code confirmed executing from the MAP_JIT region.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

Author: jeremyw

projects/unix/Makefile

@@ -246,9 +246,7 @@ ifeq ($(OS), OSX)
     endif
   endif
   ifeq ($(CPU), ARM)
-    # assembly compilation not yet supported on macOS with Apple Silicon
-    NO_ASM = 1
-    CFLAGS += -pipe -arch arm64 -mmacosx-version-min=10.16 -isysroot $(OSX_SDK_PATH)
+    CFLAGS += -pipe -arch arm64 -mmacosx-version-min=11.0 -isysroot $(OSX_SDK_PATH)
   endif
 endif
 ifeq ($(OS), MINGW)

src/device/r4300/new_dynarec/arm64/assem_arm64.c

@@ -261,9 +261,17 @@ static uintptr_t jump_table_symbols[] = {
   (intptr_t)breakpoint
 };
 
+#if defined(__APPLE__)
+#include <libkern/OSCacheControl.h>
+#endif
+
 static void cache_flush(char* start, char* end)
 {
-#ifndef WIN32
+#if defined(__APPLE__)
+    // Reading ctr_el0 from EL0 traps (SIGILL) on Apple Silicon; use the
+    // system-provided cache maintenance routine instead.
+    sys_icache_invalidate(start, end - start);
+#elif !defined(WIN32)
     // Don't rely on GCC's __clear_cache implementation, as it caches
     // icache/dcache cache line sizes, that can vary between cores on
     // big.LITTLE architectures.
@@ -4639,6 +4647,7 @@ static void arch_init(void) {
 
   // Trampolines for jumps >128MB
   intptr_t *ptr,*ptr2,*ptr3;
+  jit_write_begin();
   ptr=(intptr_t *)jump_table_symbols;
   ptr2=(intptr_t *)((char *)base_addr+(1<<TARGET_SIZE_2)-JUMP_TABLE_SIZE);
   ptr3=(intptr_t *)((char *)base_addr_rx+(1<<TARGET_SIZE_2)-JUMP_TABLE_SIZE);
@@ -4658,4 +4667,5 @@ static void arch_init(void) {
     ptr2++;
     ptr3+=2;
   }
+  jit_write_end();
 }

src/device/r4300/new_dynarec/arm64/linkage_arm64.S

@@ -18,6 +18,47 @@
  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
 
+#ifdef __APPLE__
+
+/* Mach-O: C symbols carry a leading underscore, .hidden/.type/.size are
+ * ELF-only (visibility is .private_extern), and adrp page relocations are
+ * spelled sym@PAGE/sym@PAGEOFF instead of sym/:lo12:sym. The Darwin arm64
+ * assembler treats ';' as a comment, so multi-statement macros use the '%%'
+ * statement separator instead.
+ * Each function gets two labels: _name for linkage with C code and a plain
+ * name for branches within this file. */
+
+#define GLOBAL_FUNCTION(name)      \
+    .globl _##name %%              \
+    .private_extern _##name %%     \
+    _##name: name
+
+#define LOCAL_FUNCTION(name)  \
+    name
+
+#define GLOBAL_VARIABLE(name, size_) \
+    .globl _##name %%                \
+    .private_extern _##name
+
+#define PAGE(sym)    sym@PAGE
+#define PAGEOFF(sym) sym@PAGEOFF
+
+/* C symbols referenced from this file */
+#define g_dev                _g_dev
+#define base_addr_rx         _base_addr_rx
+#define get_addr_ht          _get_addr_ht
+#define get_addr             _get_addr
+#define verify_dirty         _verify_dirty
+#define dynarec_gen_interrupt _dynarec_gen_interrupt
+#define cop1_unusable        _cop1_unusable
+#define SYSCALL_new          _SYSCALL_new
+#define ERET_new             _ERET_new
+#define dynamic_linker       _dynamic_linker
+#define dynamic_linker_ds    _dynamic_linker_ds
+#define new_recompile_block  _new_recompile_block
+
+#else /* ELF */
+
 #define GLOBAL_FUNCTION(name)  \
     .globl name;               \
     .hidden name;              \
@@ -35,6 +76,11 @@
     .type   name, %object;           \
     .size   name, size_
 
+#define PAGE(sym)    sym
+#define PAGEOFF(sym) :lo12:sym
+
+#endif
+
 .macro movl Wn, imm
     movz    \Wn, (\imm >> 16) & 0xFFFF, lsl 16
     movk    \Wn,  \imm & 0xFFFF
@@ -171,10 +217,10 @@ GLOBAL_FUNCTION(verify_code):
     mov    x21, x30 /* Save link register */
     bl     verify_dirty
     tst    x0, x0
-    b.ne   .D1
+    b.ne   1f
     mov    x30, x21 /* Restore link register */
     ret
-.D1:
+1:
     bl     get_addr
     br     x0
 
@@ -190,9 +236,9 @@ GLOBAL_FUNCTION(cc_interrupt):
     tst    w2, w2
     b.ne   new_dyna_stop
     tst    w1, w1
-    b.ne   .E1
+    b.ne   1f
     ret
-.E1:
+1:
     ldr    w0, [x29, #fp_pcaddr]
     bl     get_addr_ht
     br     x0
@@ -243,12 +289,12 @@ GLOBAL_FUNCTION(dyna_linker_ds):
     br     x0
 
 GLOBAL_FUNCTION(new_dyna_start):
-    adrp   x16, g_dev
-    add    x16, x16, :lo12:g_dev
+    adrp   x16, PAGE(g_dev)
+    add    x16, x16, PAGEOFF(g_dev)
     movl   x1, (device_r4300_new_dynarec_hot_state_dynarec_local + saved_context)
     add    x16, x16, x1
-    adrp   x1, base_addr_rx
-    add    x1, x1, :lo12:base_addr_rx
+    adrp   x1, PAGE(base_addr_rx)
+    add    x1, x1, PAGEOFF(base_addr_rx)
     mov    w0, #0xa4000000
     stp    x19,x20,[x16,#0]
     stp    x21,x22,[x16,#16]

src/device/r4300/new_dynarec/new_dynarec.c

@@ -58,6 +58,30 @@
 #include <sys/mman.h>
 #endif
 
+#if defined(__APPLE__) && defined(__aarch64__)
+/* Apple Silicon enforces W^X: the MAP_JIT code cache is executable by
+ * default and only writable while the calling thread has toggled itself
+ * into write mode with pthread_jit_write_protect_np(). Exec mode is the
+ * default; every code path that writes to the cache is bracketed with
+ * jit_write_begin/jit_write_end. The depth counter makes the brackets
+ * reentrant (e.g. dynamic_linker -> new_recompile_block). */
+#include <pthread.h>
+static int jit_write_depth;
+static void jit_write_begin(void)
+{
+  if (jit_write_depth++ == 0)
+    pthread_jit_write_protect_np(0);
+}
+static void jit_write_end(void)
+{
+  if (--jit_write_depth == 0)
+    pthread_jit_write_protect_np(1);
+}
+#else
+#define jit_write_begin() do {} while (0)
+#define jit_write_end()   do {} while (0)
+#endif
+
 #if defined(RECOMPILER_DEBUG) && !defined(RECOMP_DBG)
 void recomp_dbg_init(void);
 void recomp_dbg_cleanup(void);
@@ -2593,7 +2617,7 @@ static struct ll_entry *get_dirty(struct r4300_core* r4300,u_int vaddr,u_int fla
   return NULL;
 }
 
-void *dynamic_linker(void * src, u_int vaddr)
+static void *dynamic_linker_impl(void * src, u_int vaddr)
 {
   assert((vaddr&1)==0);
   struct r4300_core* r4300 = &g_dev.r4300;
@@ -2643,7 +2667,7 @@ void *dynamic_linker(void * src, u_int vaddr)
   }
 
   int r=new_recompile_block(vaddr);
-  if(r==0) return dynamic_linker(src,vaddr);
+  if(r==0) return dynamic_linker_impl(src,vaddr);
   // Execute in unmapped page, generate pagefault execption
   assert(r4300->cp0.tlb.LUT_r[(vaddr&~1) >> 12] == 0);
   assert((intptr_t)r4300->new_dynarec_hot_state.memory_map[(vaddr&~1) >> 12] < 0);
@@ -2652,7 +2676,15 @@ void *dynamic_linker(void * src, u_int vaddr)
   return get_addr_ht(r4300->new_dynarec_hot_state.pcaddr);
 }
 
-void *dynamic_linker_ds(void * src, u_int vaddr)
+void *dynamic_linker(void * src, u_int vaddr)
+{
+  jit_write_begin();
+  void *ret = dynamic_linker_impl(src, vaddr);
+  jit_write_end();
+  return ret;
+}
+
+static void *dynamic_linker_ds_impl(void * src, u_int vaddr)
 {
   struct r4300_core* r4300 = &g_dev.r4300;
   struct ll_entry *head;
@@ -2701,7 +2733,7 @@ void *dynamic_linker_ds(void * src, u_int vaddr)
   }
 
   int r=new_recompile_block((vaddr&0xFFFFFFF8)+1);
-  if(r==0) return dynamic_linker_ds(src,vaddr);
+  if(r==0) return dynamic_linker_ds_impl(src,vaddr);
   // Execute in unmapped page, generate pagefault execption
   assert(r4300->cp0.tlb.LUT_r[(vaddr&~1) >> 12] == 0);
   assert((intptr_t)r4300->new_dynarec_hot_state.memory_map[(vaddr&~1) >> 12] < 0);
@@ -2710,6 +2742,14 @@ void *dynamic_linker_ds(void * src, u_int vaddr)
   return get_addr_ht(r4300->new_dynarec_hot_state.pcaddr);
 }
 
+void *dynamic_linker_ds(void * src, u_int vaddr)
+{
+  jit_write_begin();
+  void *ret = dynamic_linker_ds_impl(src, vaddr);
+  jit_write_end();
+  return ret;
+}
+
 // Get address from virtual address
 // This is called from the recompiled JR/JALR instructions
 void *get_addr(u_int vaddr)
@@ -2873,7 +2913,7 @@ static void invalidate_page(u_int page)
   }
 }
 
-void invalidate_block(u_int block)
+static void invalidate_block_impl(u_int block)
 {
   u_int page;
   page=block^0x80000;
@@ -2950,11 +2990,19 @@ void invalidate_block(u_int block)
   #endif
 }
 
+void invalidate_block(u_int block)
+{
+  jit_write_begin();
+  invalidate_block_impl(block);
+  jit_write_end();
+}
+
 // This is called when loading a save state.
 // Anything could have changed, so invalidate everything.
 static void invalidate_all_pages(void)
 {
   u_int page;
+  jit_write_begin();
   for(page=0;page<4096;page++)
     invalidate_page(page);
   for(page=0;page<1048576;page++)
@@ -2967,6 +3015,7 @@ static void invalidate_all_pages(void)
   #if NEW_DYNAREC >= NEW_DYNAREC_ARM
   cache_flush((char *)base_addr_rx,(char *)base_addr_rx+(1<<TARGET_SIZE_2));
   #endif
+  jit_write_end();
   #ifdef USE_MINI_HT
   memset(g_dev.r4300.new_dynarec_hot_state.mini_ht,-1,sizeof(g_dev.r4300.new_dynarec_hot_state.mini_ht));
   #endif
@@ -8713,7 +8762,13 @@ void new_dynarec_init(void)
 #define DOUBLE_CACHE_ADDR 3   // Put the dynarec cache at random address with RW address != RX address
 
 // Default to fixed cache address
+#if defined(__APPLE__)
+// Apple Silicon requires a fresh MAP_JIT mapping for the code cache
+// (static memory cannot be made executable), so the cache address is dynamic.
+#define CACHE_ADDR DYNAMIC_CACHE_ADDR
+#else
 #define CACHE_ADDR FIXED_CACHE_ADDR
+#endif
 
 #if CACHE_ADDR==DOUBLE_CACHE_ADDR
   #include <unistd.h>
@@ -8744,7 +8799,11 @@ void new_dynarec_init(void)
 #else /*DYNAMIC_CACHE_ADDR*/
   base_addr = mmap (NULL, 1<<TARGET_SIZE_2,
                     PROT_READ | PROT_WRITE | PROT_EXEC,
-                    MAP_PRIVATE | MAP_ANONYMOUS,
+                    MAP_PRIVATE | MAP_ANONYMOUS
+#if defined(__APPLE__) && defined(__aarch64__)
+                    | MAP_JIT
+#endif
+                    ,
                     -1, 0);
   base_addr_rx = base_addr;
 #endif
@@ -8830,7 +8889,7 @@ void new_dynarec_cleanup(void)
 #endif
 }
 
-int new_recompile_block(int addr)
+static int new_recompile_block_impl(int addr)
 {
 #if defined(RECOMPILER_DEBUG) && !defined(RECOMP_DBG)
   recomp_dbg_block(addr);
@@ -11962,3 +12021,11 @@ int new_recompile_block(int addr)
   }
   return 0;
 }
+
+int new_recompile_block(int addr)
+{
+  jit_write_begin();
+  int ret = new_recompile_block_impl(addr);
+  jit_write_end();
+  return ret;
+}