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Add more Intel mitigation flags (#128)
1 parent dbe2722 commit 9e22c36

3 files changed

Lines changed: 188 additions & 174 deletions

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‎README.md‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -308,6 +308,7 @@ Exit Code 1
308308
| AVXSLOW | Indicates the CPU performs 2 128 bit operations instead of one |
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| AVXVNNI | AVX (VEX encoded) VNNI neural network instructions |
310310
| AVXVNNIINT8 | AVX-VNNI-INT8 instructions |
311+
| BHI_CTRL | Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 |
311312
| BMI1 | Bit Manipulation Instruction Set 1 |
312313
| BMI2 | Bit Manipulation Instruction Set 2 |
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| CETIBT | Intel CET Indirect Branch Tracking |
@@ -361,6 +362,7 @@ Exit Code 1
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| IBS_OPFUSE | AMD: Indicates support for IbsOpFuse |
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| IBS_PREVENTHOST | Disallowing IBS use by the host supported |
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| IBS_ZEN4 | Fetch and Op IBS support IBS extensions added with Zen4 |
365+
| IDPRED_CTRL | IPRED_DIS |
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| INT_WBINVD | WBINVD/WBNOINVD are interruptible. |
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| INVLPGB | NVLPGB and TLBSYNC instruction supported |
366368
| LAHF | LAHF/SAHF in long mode |
@@ -387,12 +389,13 @@ Exit Code 1
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| PCONFIG | PCONFIG for Intel Multi-Key Total Memory Encryption |
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| POPCNT | POPCNT instruction |
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| PPIN | AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled |
390-
| PREFETCHI | PREFETCHIT0/1 instructions |
391-
| PSFD | AMD: Predictive Store Forward Disable |
392+
| PREFETCHI | PREFETCHIT0/1 instructions |
393+
| PSFD | Predictive Store Forward Disable |
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| RDPRU | RDPRU instruction supported |
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| RDRAND | RDRAND instruction is available |
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| RDSEED | RDSEED instruction is available |
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| RDTSCP | RDTSCP Instruction |
398+
| RRSBA_CTRL | Restricted RSB Alternate |
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| RTM | Restricted Transactional Memory |
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| RTM_ALWAYS_ABORT | Indicates that the loaded microcode is forcing RTM abort. |
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| SERIALIZE | Serialize Instruction Execution |

‎cpuid.go‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,7 @@ const (
9999
AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one
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AVXVNNI // AVX (VEX encoded) VNNI neural network instructions
101101
AVXVNNIINT8 // AVX-VNNI-INT8 instructions
102+
BHI_CTRL // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598
102103
BMI1 // Bit Manipulation Instruction Set 1
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BMI2 // Bit Manipulation Instruction Set 2
104105
CETIBT // Intel CET Indirect Branch Tracking
@@ -152,6 +153,7 @@ const (
152153
IBS_OPFUSE // AMD: Indicates support for IbsOpFuse
153154
IBS_PREVENTHOST // Disallowing IBS use by the host supported
154155
IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4
156+
IDPRED_CTRL // IPRED_DIS
155157
INT_WBINVD // WBINVD/WBNOINVD are interruptible.
156158
INVLPGB // NVLPGB and TLBSYNC instruction supported
157159
LAHF // LAHF/SAHF in long mode
@@ -179,11 +181,12 @@ const (
179181
POPCNT // POPCNT instruction
180182
PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled
181183
PREFETCHI // PREFETCHIT0/1 instructions
182-
PSFD // AMD: Predictive Store Forward Disable
184+
PSFD // Predictive Store Forward Disable
183185
RDPRU // RDPRU instruction supported
184186
RDRAND // RDRAND instruction is available
185187
RDSEED // RDSEED instruction is available
186188
RDTSCP // RDTSCP Instruction
189+
RRSBA_CTRL // Restricted RSB Alternate
187190
RTM // Restricted Transactional Memory
188191
RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort.
189192
SERIALIZE // Serialize Instruction Execution
@@ -1238,7 +1241,12 @@ func support() flagSet {
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// CPUID.(EAX=7, ECX=2)
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_, _, _, edx = cpuidex(7, 2)
1244+
fs.setIf(edx&(1<<0) != 0, PSFD)
1245+
fs.setIf(edx&(1<<1) != 0, IDPRED_CTRL)
1246+
fs.setIf(edx&(1<<2) != 0, RRSBA_CTRL)
1247+
fs.setIf(edx&(1<<4) != 0, BHI_CTRL)
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fs.setIf(edx&(1<<5) != 0, MCDT_NO)
1249+
12421250
}
12431251

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// Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)

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