Robustone 0.0.0 roadmap

[luojia65]

We are pleased to set down a roadmap for Robustone 0.0.0, a Capstone-like disassembly framework. The version 0.0.0 should provide with those features:

• Full RISC-V RV64GC and RV32GC disassemble support (support all the subsets Capstone v6.0.0 supports, Ref: Prerequisite: list what RISC-V extensions are supported by the Capstone project #32)
  • RV32I and RV64I
  • RVM
  • RVA
  • RVF, RVD (ebc2baf)
  • RVC
  • Zicsr, Zicntr, Zihpm, Zicbop (Implement RISC-V Extensions: zicbop, Zicsr, Zicntr, Zihpm #34)
  • Supm
  • Ecall instruction
  • Svbare (satp), Sstvecd, Sstvala, Sscounterenw (Implement RISC-V RVA23 Supervisor extensions: Svbare, Sstvecd, Sstvala, Sscounterenw #36)
• Extra vendor RISC-V disassemble support
  • T-Head instruction sets, Support for T-Head RISC-V instruction sets #10
• Command-line tool robustone-cli with basic robustone <arch:riscv64|riscv32> <assembly-hexstring> [start-address-in-hex-format] features
• Robustone core structures and modules from robustone-core

Ref: RVA23 profile, https://github.com/riscv/riscv-profiles/releases/ ; vendor ISA manuals.

Out-of-scope features (like more ISAs, etc.) would be settled down in version 0.0.1 or later. Thanks all for support!