Attempt to build basic project for slogic16u3 board (GW5AT fpga) ends with an error

[rgerty]

# python3 -m litex_boards.targets.sipeed_slogic16u3 --build 
...
GowinSynthesis finish
Reading netlist file: "/mnt/litex/litex-boards/build/sipeed_slogic16u3/gateware/impl/gwsynthesis/project.vg"
ERROR  (PA2085) : "/mnt/litex/litex-boards/build/sipeed_slogic16u3/gateware/impl/gwsynthesis/project.vg":42937 | No 'pROM' resource in current device or using a conflict keyword 'pROM' from the primitive library
NOTE  (PA0003) : Parsing netlist file "/mnt/litex/litex-boards/build/sipeed_slogic16u3/gateware/impl/gwsynthesis/project.vg" completed with errors
NOTE  (PA0005) : Processing netlist completed with errors

From my understanding the project compiles successfully, but fails during the PnR phase with a pROM error.
Any advice?