Merge pull request #293 from cpc/llvm-22

LLVM 22 support without RISC-V

Author: pjaaskel

openasip/Makefile.am

@@ -1,12 +1,14 @@
 SUBDIRS = src data conf opset hdb compressors icdecoder_plugins \
 scripts manual cost_estimator_plugins explorer doc tools
 
-SUBDIRS += scheduler 
-SUBDIRS += bclib 
-SUBDIRS += newlib-1.17.0/tce-llvm 
-SUBDIRS += newlib-1.17.0/tcele-llvm 
+SUBDIRS += scheduler
+SUBDIRS += bclib
+SUBDIRS += newlib-1.17.0/tce-llvm
+SUBDIRS += newlib-1.17.0/tcele-llvm
 SUBDIRS += newlib-1.17.0/tcele64-llvm
+if RISCV
 SUBDIRS += newlib-1.17.0/riscv-llvm
+endif
 
 AUTOMAKE_OPTIONS = foreign
 

openasip/configure.ac

@@ -464,7 +464,7 @@ AC_PATH_PROGS([LLVM_CONFIG], [llvmtce-config llvm-config], [$llvmDir/bin])
 llvmConf=$LLVM_CONFIG
 ],
 [llvmDir=""
-AC_PATH_PROGS([LLVM_CONFIG], [llvmtce-config])
+AC_PATH_PROGS([LLVM_CONFIG], [llvmtce-config llvm-config])
 llvmConf=$LLVM_CONFIG
 ]
 )
@@ -547,6 +547,8 @@ if test x"$LLVM_INCLUDEDIR" == x/usr/include/llvm; then
 LLVM_INCLUDEDIR=/usr/include
 fi
 
+ENABLE_RISCV=true
+
 case "$LLVM_VERSION" in
      21*)
      AC_DEFINE([LLVM_21], [], "Using LLVM 21")
@@ -555,12 +557,27 @@ case "$LLVM_VERSION" in
      LLVM_SHARED_LIB_FILE=$LLVM_LIBDIR/libLLVM-$LLVM_LIBRARYVERSION$LIBRARY_SUFFIX
      LLVM_SHARED_LIB=-lLLVMTCE
      LLVM_LDFLAGS="$($llvmConf --ldflags) $LLVM_SHARED_LIB"
-     # This patch should be unnecessary in LLVM 21, it seems to have a wide
-     # range of vector datatypes up to 4096.
-     AC_DEFINE([LLVM_HAS_CUSTOM_VECTOR_EXTENSION], [2], "LLVM has the wide custom vector extension patch(wide)")
-     AC_SUBST([LLVM_HAS_CUSTOM_VECTOR_EXTENSION], ["2"])
 ;;
-
+     22.*)
+     AC_DEFINE([LLVM_22], [], "Using LLVM 22 (git)")
+     LLVM_VERSION=22
+     LLVM_LIBRARYVERSION=22git
+     LLVM_SHARED_LIB_FILE=$LLVM_LIBDIR/libLLVM-$LLVM_LIBRARYVERSION$LIBRARY_SUFFIX
+     LLVM_SHARED_LIB=-lLLVM-22git
+     LLVM_LDFLAGS="$($llvmConf --ldflags) $LLVM_SHARED_LIB"
+     # The upstream LLVM doesn't (yet) have the RISC-V customization support.
+     ENABLE_RISCV=false
+;;
+     23.*)
+     AC_DEFINE([LLVM_23], [], "Using LLVM 23 (git)")
+     LLVM_VERSION=23
+     LLVM_LIBRARYVERSION=23git
+     LLVM_SHARED_LIB_FILE=$LLVM_LIBDIR/libLLVM-$LLVM_LIBRARYVERSION$LIBRARY_SUFFIX
+     LLVM_SHARED_LIB=-lLLVM-23git
+     LLVM_LDFLAGS="$($llvmConf --ldflags) $LLVM_SHARED_LIB"
+     # The upstream LLVM doesn't (yet) have the RISC-V customization support.
+     ENABLE_RISCV=false
+;;
      *)
    AC_MSG_NOTICE(
    [
@@ -577,6 +594,15 @@ AC_MSG_NOTICE([
 ])
 
 
+AM_CONDITIONAL([RISCV], test x$ENABLE_RISCV = xtrue)
+
+
+# The patch for SIMD is not needed any more in the recent LLVMs.
+# TODO: remove this macro.
+AC_DEFINE([LLVM_HAS_CUSTOM_VECTOR_EXTENSION], [2],
+"LLVM has the wide custom vector extension patch(wide)")
+AC_SUBST([LLVM_HAS_CUSTOM_VECTOR_EXTENSION], ["2"])
+
 if test ! -e $LLVM_SHARED_LIB_FILE;
 then
   # Try the alternative location where llvm.org/apt packages install it.
@@ -1567,6 +1593,9 @@ $srcdir/newlib-1.17.0/configure --prefix=$prefix --target=tcele64-llvm --disable
 2>&1 | egrep -v "to force reconfigure";
 ])
 
+if test x$ENABLE_RISCV = xtrue;
+then
+
 AC_CONFIG_COMMANDS_POST ([
 echo "=== Configuring newlib for riscv =====";
 # make srcdir absolute
@@ -1587,6 +1616,16 @@ $srcdir/newlib-1.17.0/configure --prefix=$prefix --target=riscv --disable-multil
 2>&1 | egrep -v "to force reconfigure";
 ])
 
+rm -f ../testsuite/systemtest_long/bintools/RISCV/tcetest_custom_ops.sh.disabled
+rm -f ../testsuite/systemtest_long/procgen/RISCV/tcetest_stdlib.sh.disabled
+
+else
+
+touch ../testsuite/systemtest_long/bintools/RISCV/tcetest_custom_ops.sh.disabled
+touch ../testsuite/systemtest_long/procgen/RISCV/tcetest_stdlib.sh.disabled
+
+fi
+
 # Generate config.status and launch it. config.status then
 # performs all configuration actions.
 AC_OUTPUT
@@ -1646,7 +1685,7 @@ if test x"$LLVM_VERSION" = x
 then
   echo "NOTE! Supported LLVM version not found. Compiling C programs is disabled."
 else
-  echo "Found LLVM version $LLVM_VERSION"
+  echo "Found LLVM version $LLVM_VERSION".
 fi
 
 

openasip/src/applibs/LLVMBackend/LLVMBackend.cc

@@ -621,9 +621,9 @@ LLVMBackend::compile(
     std::string featureString ="";
 
     // run registering code, which should have been done by LLVM
-    
-    // Initialize targets first. needs 
-    // #include <llvm/Target/TargetSelecty.h>, 
+
+    // Initialize targets first. needs
+    // #include <llvm/Target/TargetSelecty.h>,
     // whose defines collide with tce_config.h
 
     //InitializeAllTargets();
@@ -633,9 +633,11 @@ LLVMBackend::compile(
     LLVMInitializeTCETargetInfo();
     LLVMInitializeTCETarget();
 
+    llvm::Triple targetTriple(targetStr);
+
     // get registered target machine and set plugin.
     const Target* tceTarget =
-        TargetRegistry::lookupTarget(targetStr, errorStr);
+        TargetRegistry::lookupTarget(targetTriple, errorStr);
     Target* nonconst_target = const_cast<Target*>(tceTarget);
 
     if (!tceTarget) {
@@ -653,7 +655,9 @@ LLVMBackend::compile(
     std::string cpuStr = "tce";
 
     TargetOptions Options;
+#if LLVM_MAJOR_VERSION < 22
     Options.UnsafeFPMath = false; //EnableUnsafeFPMath;
+#endif
     Options.NoInfsFPMath = false; //EnableNoInfsFPMath;
     Options.NoNaNsFPMath = false; //EnableNoNaNsFPMath;
     Options.HonorSignDependentRoundingFPMathOption = false;
@@ -684,10 +688,9 @@ LLVMBackend::compile(
     Options.GuaranteedTailCallOpt = true; //EnableGuaranteedTailCallOpt;
 
     TCETargetMachine* targetMachine =
-        static_cast<TCETargetMachine*>(
-            tceTarget->createTargetMachine(
-                targetStr, cpuStr, featureString, Options,
-                Reloc::Model::Static));
+        static_cast<TCETargetMachine*>(tceTarget->createTargetMachine(
+            targetTriple, cpuStr, featureString, Options,
+            Reloc::Model::Static));
 
     if (!targetMachine) {
         errs() << "Could not create tce target machine" << "\n";

openasip/src/applibs/LLVMBackend/LowerMissingInstructions.cc

@@ -27,6 +27,10 @@
  * Convert instruction which are not supported by the machine to
  * function calls.
  *
+ * We perform this because there is no binary linker in the compiler chain
+ * which would be required by the regular libcall conversion in the LLVM
+ * code generation.
+ *
  * NOTE: Right now system is limited to replace only those operations, which
  *       use only one bitwidth integers for example i1.icmp.i32.i32 cannot
  *       be lowered to function call.

openasip/src/applibs/LLVMBackend/TCEStubSubTarget.cc

@@ -43,16 +43,14 @@ using namespace llvm;
 TCEStubSubTarget::TCEStubSubTarget(
     const Triple& TT, const StringRef& CPU, const StringRef& FS,
     const TCEStubTargetMachine& TM)
-    :
-#if LLVM_MAJOR_VERSION < 21
-      TargetSubtargetInfo(
-          TT, CPU, FS, FS, ArrayRef<SubtargetFeatureKV>(),
-          ArrayRef<SubtargetSubTypeKV>(), NULL, NULL, NULL, NULL, NULL, NULL),
-#else
-      TargetSubtargetInfo(
+    : TargetSubtargetInfo(
           TT, CPU, FS, FS, llvm::ArrayRef<llvm::StringRef>(),
           ArrayRef<SubtargetFeatureKV>(), ArrayRef<SubtargetSubTypeKV>(),
           NULL, NULL, NULL, NULL, NULL, NULL),
+#if LLVM_MAJOR_VERSION < 22
+      TLI(TM)
+#else
+      TLI(TM, *this)
 #endif
-      TLI(TM) {
+{
 }

openasip/src/applibs/LLVMBackend/TDGen.cc

@@ -1068,7 +1068,7 @@ TDGen::write32bitRegisterInfo(std::ostream& o) {
     for (; i < regs32bit_.size(); i++) {
         std::string regName = "I" + Conversion::toString(i);
         writeRegisterDef(o, regs32bit_[i], regName, "R32", "", GPR);
-        
+
         if (!regsInRFClasses_.count(regs32bit_[i].rf)) {
             regsInRFClasses_[regs32bit_[i].rf] = std::vector<std::string>();
         }
@@ -1078,12 +1078,12 @@ TDGen::write32bitRegisterInfo(std::ostream& o) {
     }
 
     o << std::endl;
-    
+
     if (!mach_.is64bit()) {
         // Bypass registers
         for (size_t j = 0; j < 256; ++j) {
             std::string regName = "BP" + Conversion::toString(j);
-            
+
             o << "def " << regName << " : " 
               << "R32<\"ByPass_Regs" 
               << "\", []>, DwarfRegNum<"
@@ -3575,13 +3575,23 @@ TDGen::writeInstrInfo(std::ostream& os) {
     createConstantMaterializationPatterns(os);
     createConstShiftPatterns(os);
     createBoolAndHalfLoadPatterns(os);
+
+    os << std::endl;
+#if LLVM_MAJOR_VERSION > 21
+    if (mach_.is64bit())
+        os << "defm : RemapAllTargetPseudoPointerOperands<R64IRegs>;"
+           << std::endl;
+    else
+        os << "defm : RemapAllTargetPseudoPointerOperands<R32IRegs>;"
+           << std::endl;
+#endif
 }
 
 void TDGen::writeCallDefRegs(std::ostream& o) {
     for (unsigned i = 0; i < resRegNames_.size(); i++) {
         if (i > 0) o << ", ";
         o << resRegNames_[i];
-    }    
+    }
     for (unsigned i = 0; i < gprRegNames_.size(); i++) {
         o << ", " << gprRegNames_[i];
     }

openasip/src/applibs/LLVMBackend/passes/LowerIntrinsics.cc

@@ -49,7 +49,11 @@ IGNORE_COMPILER_WARNING("-Wunused-parameter")
 #include <llvm/IR/Function.h>
 #include <llvm/Pass.h>
 #include <llvm/Passes/PassBuilder.h>
+#if LLVM_MAJOR_VERSION < 22
 #include <llvm/Passes/PassPlugin.h>
+#else
+#include <llvm/Plugins/PassPlugin.h>
+#endif
 #include <llvm/CodeGen/IntrinsicLowering.h>
 
 POP_COMPILER_DIAGS

openasip/src/applibs/LLVMBackend/plugin/TCEDAGToDAGISel.cc

@@ -58,6 +58,8 @@ class TCEDAGToDAGISel : public llvm::SelectionDAGISel {
 public:
     static char ID;
 
+    TCEDAGToDAGISel() = delete;
+
     explicit TCEDAGToDAGISel(llvm::TCETargetMachine& tm);
     virtual ~TCEDAGToDAGISel();