Merge pull request #299 from cpc/endianess-fix

Endianess fix

Author: pjaaskel

openasip/CHANGES

@@ -10,6 +10,9 @@ Main changes and features
   instruction selection for RISC-V custom instructions.
 - Added feature to generate SFUs with RISC-V custom instructions 
   that can be interfaced with CV-X and ROCC interfaces, utilizing FUGen.
+- Added register file generator (RFGen), which allows RF RTL to be directly
+  generated from ADF descriptions. Verilog and VHDL supported.
+- Improved Verilog RTL generation, especially in FUGen.
 
 Deprecation notice
 ------------------

openasip/src/tools/LLVMIRTools.cc

@@ -111,10 +111,10 @@ std::string
 LLVMIRTools::targetInfo(bool littleEndian) const {
     std::string targetInfoStr = "target datalayout = \"";
     if(littleEndian){
-        targetInfoStr += DataLayoutStringBE;
+        targetInfoStr += DataLayoutStringLE;
     }
     else{
-        targetInfoStr += DataLayoutStringLE;
+        targetInfoStr += DataLayoutStringBE;
     }
     targetInfoStr += "\"\n";
     targetInfoStr += std::string("target triple = \"")