From 827dd45adc3224cfb874f615efecf2c779981166 Mon Sep 17 00:00:00 2001 From: Martina Date: Mon, 11 May 2026 11:02:12 +0200 Subject: [PATCH 1/9] BTL cabling mapping --- CondFormats/MTDObjects/BuildFile.xml | 4 + .../interface/BTLElectronicsMapping.h | 333 ++++++++++++++++++ .../MTDObjects}/src/BTLElectronicsMapping.cc | 207 +++++++++-- CondFormats/MTDObjects/test/BuildFile.xml | 15 + .../test/TestBTLElectronicsMapping.cc | 185 ++++++++++ .../test/testBTLElectronicsMapping.py | 41 +++ .../interface/BTLElectronicsMapping.h | 86 ----- .../test/DD4hep_TestMTDIdealGeometry.cc | 16 +- 8 files changed, 770 insertions(+), 117 deletions(-) create mode 100644 CondFormats/MTDObjects/BuildFile.xml create mode 100644 CondFormats/MTDObjects/interface/BTLElectronicsMapping.h rename {Geometry/MTDCommonData => CondFormats/MTDObjects}/src/BTLElectronicsMapping.cc (52%) create mode 100644 CondFormats/MTDObjects/test/BuildFile.xml create mode 100644 CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc create mode 100644 CondFormats/MTDObjects/test/testBTLElectronicsMapping.py delete mode 100644 Geometry/MTDCommonData/interface/BTLElectronicsMapping.h diff --git a/CondFormats/MTDObjects/BuildFile.xml b/CondFormats/MTDObjects/BuildFile.xml new file mode 100644 index 0000000000000..2aad656760105 --- /dev/null +++ b/CondFormats/MTDObjects/BuildFile.xml @@ -0,0 +1,4 @@ + + + + diff --git a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h new file mode 100644 index 0000000000000..1d79b3751555e --- /dev/null +++ b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h @@ -0,0 +1,333 @@ +#ifndef DATAFORMATS_BTLELECTRONICSMAPPING_H +#define DATAFORMATS_BTLELECTRONICSMAPPING_H 1 + +#include +#include + +#include "DataFormats/ForwardDetId/interface/BTLDetId.h" +#include + +/** \brief BTL TOFHIR channel mapping with crystal BTLDetId + Convention: + SiPMside 0 == Minus Side + SiPMside 1 == Plus Side + */ + +class BTLElectronicsMapping { +public: + struct SiPMChPair { + int Minus; + int Plus; + }; + + struct TOFHIRChPair { + int Minus; + int Plus; + }; + + // Map SiPM Channel to crystal bars for Forward module orientation + static constexpr std::array SiPMChannelMapFW{ + {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0}}; + // Map SiPM Channel to crystal bars for Backward module orientation + static constexpr std::array SiPMChannelMapBW{ + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16}}; + + // Map TOFHIR Channel to SiPM Channel + static constexpr std::array THChannelMap{ + {4, 1, 0, 3, 2, 6, 7, 9, 5, 11, 8, 12, 10, 14, 15, 13, + 17, 16, 18, 19, 20, 23, 21, 26, 22, 27, 28, 31, 30, 24, 25, 29}}; + + /** Default constructor -- invalid value */ + BTLElectronicsMapping(const BTLDetId::CrysLayout lay); + + // Get SiPM Channel number from crystal + int SiPMCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide) const; + int SiPMCh(BTLDetId det, uint32_t SiPMSide) const; + int SiPMCh(uint32_t rawID, uint32_t SiPMSide) const; + + SiPMChPair GetSiPMChPair(uint32_t smodCopy, uint32_t crystal) const; + SiPMChPair GetSiPMChPair(BTLDetId det) const; + SiPMChPair GetSiPMChPair(uint32_t rawID) const; + + // Get TOFHIR Channel number from crystal + int TOFHIRCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide) const; + int TOFHIRCh(BTLDetId det, uint32_t SiPMSide) const; + int TOFHIRCh(uint32_t rawID, uint32_t SiPMSide) const; + + TOFHIRChPair GetTOFHIRChPair(uint32_t smodCopy, uint32_t crystal) const; + TOFHIRChPair GetTOFHIRChPair(BTLDetId det) const; + TOFHIRChPair GetTOFHIRChPair(uint32_t rawID) const; + + // Get xtal from TOFHIR Channel number + int THChToXtal(uint32_t smodCopy, uint32_t THCh) const; + BTLDetId THChToBTLDetId( + uint32_t zside, uint32_t rod, uint32_t runit, uint32_t dmodule, uint32_t smodCopy, uint32_t THCh) const; + + /** Returns TOFHIR ASIC number in construction database. */ + int TOFHIRASIC(uint32_t dmodule, uint32_t smodCopy) const; + int TOFHIRASIC(BTLDetId det) const; + int TOFHIRASIC(uint32_t rawID) const; + + /** Returns FE board number */ + int FEBoardFromDM(uint32_t dmodule) const; + int FEBoard(BTLDetId det) const; + int FEBoard(uint32_t rawID) const; + + /** Returns CC board number */ + int CCBoardFromRU(uint32_t dmodule) const; + int CCBoard(BTLDetId det) const; + int CCBoard(uint32_t rawID) const; + + + /** ======== DAQ cabling mapping ========== **/ + /** E-LINK <-> TOFHIR/SM **/ + /** HS-link <-> CC/RU to Serenity **/ + /** S-link <-> FED Id (6 trays) **/ + /** ======================================= **/ + + /** E-LINK **/ + /** E-LINK identifies which TOFHIR/SM within a CC. The mapping depends if lpgbt L0 or L1 is used. Default is L0. **/ + /** Ref: https://gitlab.cern.ch/btl-commissioning/mtd_daq/-/blob/tif_new_s1p2/src/mtd_daq/configurator/mappings.py?ref_type=heads#L79-130 */ + + static constexpr std::array, BTLDetId::kDModulesPerRU*2 > ELINK_to_FE_mapping_L0{ + {{7, 1}, // e-link 0: {DM 7, chipId 1} + {7, 0}, // e-link 1: {DM 7, chipId 0} + {3, 1}, + {3, 0}, + {2, 1}, + {2, 0}, + {0, 0}, + {0, 1}, + {1, 1}, + {1, 0}, + {5, 0}, + {5, 1}, + {4, 1}, + {4, 0}, + {8, 0}, + {9, 1}, + {9, 0}, + {8, 1}, + {10, 0}, + {10, 1}, + {11, 1}, + {11, 0}, + {6, 1}, + {6, 0} // e-link 23: {DM 6, chipId 0} + }}; + + static constexpr std::array, BTLDetId::kDModulesPerRU*2> ELINK_to_FE_mapping_L1{ + {{6, 1}, // e-link 0: {DM 6, chipId 1} + {3, 1}, // e-link 1: {DM 3, chipId 1} + {11, 0}, + {11, 1}, + {3, 0}, + {6, 0}, + {2, 1}, + {2, 0}, + {1, 0}, + {1, 1}, + {0, 0}, + {0, 1}, + {5, 1}, + {5, 0}, + {4, 0}, + {4, 1}, + {9, 1}, + {9, 0}, + {8, 0}, + {8, 1}, + {10, 0}, + {10, 1}, + {11, 0}, + {11, 1} // e-link 23: {DM 11, chipId 1} + }}; + + // ELINK Reverse mapping: given an FE/DM (0-11) and a ChipId (0-1), find the corresponding e-link + static constexpr auto buildFEtoElinkMapping = [](auto const& mapping) { + std::array, BTLDetId::kDModulesPerRU > tmp {}; // pair is (DM, chipId), there are 12 pairs. + for (auto& row : tmp) row.fill(-1);// initialize to -1 + for (unsigned int elink = 0; elink < BTLDetId::kDModulesPerRU*2; ++elink) { + tmp[mapping[elink].first][mapping[elink].second] = static_cast(elink); + } + return tmp; + }; + + static constexpr auto FE_to_ELINK_mapping_L0 = buildFEtoElinkMapping(ELINK_to_FE_mapping_L0); + static constexpr auto FE_to_ELINK_mapping_L1 = buildFEtoElinkMapping(ELINK_to_FE_mapping_L1); + + // -- Get the e-link for a given SM + int elinkFromSM(uint32_t dmodule, uint32_t smodCopy, int lpgbt_id = 0) const; // e-link from DM and SM + int elink(BTLDetId det, int lpgbt_id = 0) const; // e-link from BTLDetId + int elink(uint32_t rawID, int lpgbt_id = 0) const; // e-link from rawID + // -- Get the (DM,SM) for a given e-link + std::pair elinkToSM(int elink, int lpgbt_id = 0) const; + + // ** HS-LINK **/ + // ** HS-link = link CC/RU to Serenity **/ + // Mapping of FPGA Tx port number (hs-link) to optical Tx channels provided by O. Sahin. + // Note: this mapping is not strictly sequential!!! + // In totale there are 72 = 6 x 12 hs-links (from 4 to 75) in blocks of 12. Each block will correspond to one tray. + // Within each block: + // Opt Tx 0, 2, 4, 6, 8, 10 --> correspond to CC 0,1,2,3,4,5 for LPGBT0 + // Opt Tx 1, 3, 5, 7, 9, 11 --> correspond to CC 0,1,2,3,4,5 for LPGBT1 + // !!!! Which tray goes to which block for now is arbitrary, but for the fact that 6 trays are contiguos + // TEMPORARY MAPPING: within a group of 6 trays ( = supertray): tray 0 --> first block of 12 links, tray 1--> second block of 12 links, etc. + // For the first block (FF_N5), channel ids of the optical tx are reversed. + + /* struct Tx { + const char* name; + int index; + }; + + static constexpr std::array Tx_map = {{ + {}, {}, {}, {}, // 0-3 unused + + // FF_N5_tx (4-15) + { "FF_N5_tx", 1 }, // 4 + { "FF_N5_tx", 3 }, // 5 + { "FF_N5_tx", 5 }, // 6 + { "FF_N5_tx", 0 }, // 7 + { "FF_N5_tx", 2 }, // 8 + { "FF_N5_tx", 4 }, // 9 + { "FF_N5_tx", 6 }, // 10 + { "FF_N5_tx", 8 }, // 11 + { "FF_N5_tx", 10 }, // 12 + { "FF_N5_tx", 7 }, // 13 + { "FF_N5_tx", 9 }, // 14 + { "FF_N5_tx", 11 }, // 15 + + // FF_S0_tx (16 - 27) + { "FF_S0_tx", 11 }, // 16 + { "FF_S0_tx", 9 }, // 17 + { "FF_S0_tx", 7 }, // 18 + { "FF_S0_tx", 10 }, // 19 + { "FF_S0_tx", 8 }, // 20 + { "FF_S0_tx", 6 }, // 21 + { "FF_S0_tx", 4 }, // 22 + { "FF_S0_tx", 2 }, // 23 + { "FF_S0_tx", 0 }, // 24 + { "FF_S0_tx", 5 }, // 25 + { "FF_S0_tx", 3 }, // 26 + { "FF_S0_tx", 1 }, // 27 + + // FF_S1_tx (28 - 39) + { "FF_S1_tx", 11 }, // 28 + { "FF_S1_tx", 9 }, // 29 + { "FF_S1_tx", 7 }, // 30 + { "FF_S1_tx", 10 }, // 31 + { "FF_S1_tx", 8 }, // 32 + { "FF_S1_tx", 6 }, // 33 + { "FF_S1_tx", 4 }, // 34 + { "FF_S1_tx", 2 }, // 35 + { "FF_S1_tx", 0 }, // 36 + { "FF_S1_tx", 5 }, // 37 + { "FF_S1_tx", 3 }, // 38 + { "FF_S1_tx", 1 }, // 39 + + // FF_S2_tx (40 - 51) + { "FF_S2_tx", 11 }, // 40 + { "FF_S2_tx", 9 }, // 41 + { "FF_S2_tx", 7 }, // 42 + { "FF_S2_tx", 10 }, // 43 + { "FF_S2_tx", 8 }, // 44 + { "FF_S2_tx", 6 }, // 45 + { "FF_S2_tx", 4 }, // 46 + { "FF_S2_tx", 2 }, // 47 + { "FF_S2_tx", 0 }, // 48 + { "FF_S2_tx", 5 }, // 49 + { "FF_S2_tx", 3 }, // 50 + { "FF_S2_tx", 1 }, // 51 + + // FF_S3_tx (52 - 63) + { "FF_S3_tx", 11 }, // 52 + { "FF_S3_tx", 9 }, // 53 + { "FF_S3_tx", 7 }, // 54 + { "FF_S3_tx", 10 }, // 55 + { "FF_S3_tx", 8 }, // 56 + { "FF_S3_tx", 6 }, // 57 + { "FF_S3_tx", 4 }, // 58 + { "FF_S3_tx", 2 }, // 59 + { "FF_S3_tx", 0 }, // 60 + { "FF_S3_tx", 5 }, // 61 + { "FF_S3_tx", 3 }, // 62 + { "FF_S3_tx", 1 }, // 63 + + // FF_N4_tx (64 - 75) + { "FF_N4_tx", 11 }, // 64 + { "FF_N4_tx", 9 }, // 65 + { "FF_N4_tx", 7 }, // 66 + { "FF_N4_tx", 10 }, // 67 + { "FF_N4_tx", 8 }, // 68 + { "FF_N4_tx", 6 }, // 69 + { "FF_N4_tx", 4 }, // 70 + { "FF_N4_tx", 2 }, // 71 + { "FF_N4_tx", 0 }, // 72 + { "FF_N4_tx", 5 }, // 73 + { "FF_N4_tx", 3 }, // 74 + { "FF_N4_tx", 1 } // 75 + }}; + + */ + + static constexpr uint32_t kNumHSLinks = 72; // number of HS links: in each Serenity 6 trays x 12 links + static constexpr uint32_t kOffsetHSLinks = 4; // offset (HS link Ids start from 4 (0-3 reserved) + static constexpr uint32_t MIN_SLINK_ID = 1000; // arbitrary for now + + + // Define an array of 12 elements, each element is the optical Tx channel Id (this depends on the FF). Then each channel will map to a CC/RU + static constexpr std::array optTxCh_n5 = { 1, 3, 5, 0, 2, 4, 6, 8, 10, 7, 9, 11}; // 12 = 6 RUs x 2 LPGBTs + static constexpr std::array optTxCh_common = { 11, 9, 7, 10, 8, 6, 4, 2, 0, 5, 3, 1};// 12 = 6 RUs x 2 LPGBTs + + static constexpr auto OptTx_map = []() { + std::array tmp; + tmp.fill(-1); + for (unsigned int i = 0; i < kNumHSLinks / 12; i++) { + for (int j = 0; j < 12; j++) { + int hslink_id = kOffsetHSLinks + i * 12 + j; + tmp[hslink_id] = (i == 0) ? optTxCh_n5[j] : optTxCh_common[j]; + } + } + return tmp; + }(); + + + // Build inverse mapping + static constexpr auto tx_to_index = [](const std::array& p) { + std::array inv{}; + inv.fill(-1); + for (int i = 0; i < 12; ++i) + inv[p[i]] = i; + return inv; + }; + static constexpr auto tx_inv_n5 = tx_to_index(optTxCh_n5); + static constexpr auto tx_inv_common = tx_to_index(optTxCh_common); + + // -- Get the CC/RU corresponding to a given HS-link + int hslinkToRU(int hslink) const; + // -- Get the HS-link corresponding to a given RU/CC in a tray + int hslinkFromRU(uint32_t runit, uint32_t tray, int lpgbt_id = 0) const; + int hslink(BTLDetId det, int lpgbt_id = 0) const; + int hslink(uint32_t rawID, int lpgbt_id = 0) const; + + + /** S-link **/ + /** one S-link corresponds to a group of 6 trays. one S-link = one FEDId **/ + /** !!!!! TEMPORARY mapping for now until FEDId not assigned !!!!! **/ + // TEMPORARY MAPPING: // trays [0-35], z- --> Slinks [0,5] + // trays [0-35], z+ --> Slinks [6,11] + + // -- Get the tray Id from combination of S-link (--> group fo 6 trays) and HS-link (which tray in that S-link, i.e. + std::pair getTrayFromLinks(int slink, int hslink) const; // return tray number [0-35] and z side [0,1] given S-link and HS-link Id + // -- Get the S-link for a given tray + int SlinkFromTray(uint32_t tray, uint32_t zside) const; + int Slink(BTLDetId det) const; + int Slink(uint32_t rawID) const; + + +private: +}; + +#endif diff --git a/Geometry/MTDCommonData/src/BTLElectronicsMapping.cc b/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc similarity index 52% rename from Geometry/MTDCommonData/src/BTLElectronicsMapping.cc rename to CondFormats/MTDObjects/src/BTLElectronicsMapping.cc index 5a487645f1c25..ef881f2993c2f 100644 --- a/Geometry/MTDCommonData/src/BTLElectronicsMapping.cc +++ b/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc @@ -1,5 +1,6 @@ #include "FWCore/MessageLogger/interface/MessageLogger.h" -#include "Geometry/MTDCommonData/interface/BTLElectronicsMapping.h" +//#include "Geometry/MTDCommonData/interface/BTLElectronicsMapping.h" +#include "CondFormats/MTDObjects/interface/BTLElectronicsMapping.h" #include "FWCore/Utilities/interface/Exception.h" #include @@ -16,7 +17,7 @@ BTLElectronicsMapping::BTLElectronicsMapping(const BTLDetId::CrysLayout lay) { // Get SiPM Channel from crystal ID -int BTLElectronicsMapping::SiPMCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide) { +int BTLElectronicsMapping::SiPMCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide) const{ if (0 > int(crystal) || crystal > BTLDetId::kCrystalsPerModuleV2) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::BTLElectronicsMapping(): " << "****************** Bad crystal number = " << int(crystal); @@ -35,32 +36,32 @@ int BTLElectronicsMapping::SiPMCh(uint32_t smodCopy, uint32_t crystal, uint32_t return BTLElectronicsMapping::SiPMChannelMapBW[crystal + SiPMSide * BTLDetId::kCrystalsPerModuleV2]; } -int BTLElectronicsMapping::SiPMCh(BTLDetId det, uint32_t SiPMSide) { +int BTLElectronicsMapping::SiPMCh(BTLDetId det, uint32_t SiPMSide) const { uint32_t smodCopy = det.smodule(); uint32_t crystal = det.crystal(); return BTLElectronicsMapping::SiPMCh(smodCopy, crystal, SiPMSide); } -int BTLElectronicsMapping::SiPMCh(uint32_t rawId, uint32_t SiPMSide) { +int BTLElectronicsMapping::SiPMCh(uint32_t rawId, uint32_t SiPMSide) const { BTLDetId theId(rawId); return BTLElectronicsMapping::SiPMCh(theId, SiPMSide); } -BTLElectronicsMapping::SiPMChPair BTLElectronicsMapping::GetSiPMChPair(uint32_t smodCopy, uint32_t crystal) { +BTLElectronicsMapping::SiPMChPair BTLElectronicsMapping::GetSiPMChPair(uint32_t smodCopy, uint32_t crystal) const { BTLElectronicsMapping::SiPMChPair SiPMChs; SiPMChs.Minus = BTLElectronicsMapping::SiPMCh(smodCopy, crystal, 0); SiPMChs.Plus = BTLElectronicsMapping::SiPMCh(smodCopy, crystal, 1); return SiPMChs; } -BTLElectronicsMapping::SiPMChPair BTLElectronicsMapping::GetSiPMChPair(BTLDetId det) { +BTLElectronicsMapping::SiPMChPair BTLElectronicsMapping::GetSiPMChPair(BTLDetId det) const { BTLElectronicsMapping::SiPMChPair SiPMChs; SiPMChs.Minus = BTLElectronicsMapping::SiPMCh(det, 0); SiPMChs.Plus = BTLElectronicsMapping::SiPMCh(det, 1); return SiPMChs; } -BTLElectronicsMapping::SiPMChPair BTLElectronicsMapping::GetSiPMChPair(uint32_t rawID) { +BTLElectronicsMapping::SiPMChPair BTLElectronicsMapping::GetSiPMChPair(uint32_t rawID) const { BTLElectronicsMapping::SiPMChPair SiPMChs; SiPMChs.Minus = BTLElectronicsMapping::SiPMCh(rawID, 0); SiPMChs.Plus = BTLElectronicsMapping::SiPMCh(rawID, 1); @@ -69,37 +70,37 @@ BTLElectronicsMapping::SiPMChPair BTLElectronicsMapping::GetSiPMChPair(uint32_t // Get TOFHIR Channel from crystal ID -int BTLElectronicsMapping::TOFHIRCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide) { +int BTLElectronicsMapping::TOFHIRCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide) const { int SiPMCh_ = BTLElectronicsMapping::SiPMCh(smodCopy, crystal, SiPMSide); return BTLElectronicsMapping::THChannelMap[SiPMCh_]; } -int BTLElectronicsMapping::TOFHIRCh(BTLDetId det, uint32_t SiPMSide) { +int BTLElectronicsMapping::TOFHIRCh(BTLDetId det, uint32_t SiPMSide) const { uint32_t smodCopy = det.smodule(); uint32_t crystal = det.crystal(); return BTLElectronicsMapping::TOFHIRCh(smodCopy, crystal, SiPMSide); } -int BTLElectronicsMapping::TOFHIRCh(uint32_t rawId, uint32_t SiPMSide) { +int BTLElectronicsMapping::TOFHIRCh(uint32_t rawId, uint32_t SiPMSide) const { BTLDetId theId(rawId); return BTLElectronicsMapping::TOFHIRCh(theId, SiPMSide); } -BTLElectronicsMapping::TOFHIRChPair BTLElectronicsMapping::GetTOFHIRChPair(uint32_t smodCopy, uint32_t crystal) { +BTLElectronicsMapping::TOFHIRChPair BTLElectronicsMapping::GetTOFHIRChPair(uint32_t smodCopy, uint32_t crystal) const { BTLElectronicsMapping::TOFHIRChPair TOFHIRChs; TOFHIRChs.Minus = BTLElectronicsMapping::TOFHIRCh(smodCopy, crystal, 0); TOFHIRChs.Plus = BTLElectronicsMapping::TOFHIRCh(smodCopy, crystal, 1); return TOFHIRChs; } -BTLElectronicsMapping::TOFHIRChPair BTLElectronicsMapping::GetTOFHIRChPair(BTLDetId det) { +BTLElectronicsMapping::TOFHIRChPair BTLElectronicsMapping::GetTOFHIRChPair(BTLDetId det) const { BTLElectronicsMapping::TOFHIRChPair TOFHIRChs; TOFHIRChs.Minus = BTLElectronicsMapping::TOFHIRCh(det, 0); TOFHIRChs.Plus = BTLElectronicsMapping::TOFHIRCh(det, 1); return TOFHIRChs; } -BTLElectronicsMapping::TOFHIRChPair BTLElectronicsMapping::GetTOFHIRChPair(uint32_t rawID) { +BTLElectronicsMapping::TOFHIRChPair BTLElectronicsMapping::GetTOFHIRChPair(uint32_t rawID) const { BTLElectronicsMapping::TOFHIRChPair TOFHIRChs; TOFHIRChs.Minus = BTLElectronicsMapping::TOFHIRCh(rawID, 0); TOFHIRChs.Plus = BTLElectronicsMapping::TOFHIRCh(rawID, 1); @@ -108,7 +109,7 @@ BTLElectronicsMapping::TOFHIRChPair BTLElectronicsMapping::GetTOFHIRChPair(uint3 // Get crystal ID from TOFHIR Channel -int BTLElectronicsMapping::THChToXtal(uint32_t smodCopy, uint32_t THCh) { +int BTLElectronicsMapping::THChToXtal(uint32_t smodCopy, uint32_t THCh) const { if (0 > int(smodCopy) || BTLDetId::kSModulesPerDM < smodCopy) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::getUnitID(): " << "****************** Bad detector module copy = " << int(smodCopy); @@ -130,7 +131,7 @@ int BTLElectronicsMapping::THChToXtal(uint32_t smodCopy, uint32_t THCh) { } BTLDetId BTLElectronicsMapping::THChToBTLDetId( - uint32_t zside, uint32_t rod, uint32_t runit, uint32_t dmodule, uint32_t smodCopy, uint32_t THCh) { + uint32_t zside, uint32_t rod, uint32_t runit, uint32_t dmodule, uint32_t smodCopy, uint32_t THCh) const { if (0 > int(THCh) || 31 < THCh) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::getUnitID(): " << "****************** Bad TOFHIR channel = " << int(THCh); @@ -173,46 +174,204 @@ BTLDetId BTLElectronicsMapping::THChToBTLDetId( // else if dmodule is even number the order is inverted // SM1 --> TOFHIR A1 (simply 1) // SM2 --> TOFHIR A0 (simply 0) -int BTLElectronicsMapping::TOFHIRASIC(uint32_t dmodule, uint32_t smodCopy) { +int BTLElectronicsMapping::TOFHIRASIC(uint32_t dmodule, uint32_t smodCopy) const { if (dmodule % BTLDetId::kSModulesInDM == 0) return smodCopy; else return BTLDetId::kSModulesInDM - smodCopy - 1; } -int BTLElectronicsMapping::TOFHIRASIC(BTLDetId det) { +int BTLElectronicsMapping::TOFHIRASIC(BTLDetId det) const { uint32_t dmodule = det.dmodule(); uint32_t smodCopy = det.smodule(); return BTLElectronicsMapping::TOFHIRASIC(dmodule, smodCopy); } -int BTLElectronicsMapping::TOFHIRASIC(uint32_t rawID) { +int BTLElectronicsMapping::TOFHIRASIC(uint32_t rawID) const { BTLDetId theId(rawID); return BTLElectronicsMapping::TOFHIRASIC(theId); } /** Returns FE board number */ -int BTLElectronicsMapping::FEBoardFromDM(uint32_t dmodule) { return dmodule; } +int BTLElectronicsMapping::FEBoardFromDM(uint32_t dmodule) const { return dmodule; } -int BTLElectronicsMapping::FEBoard(BTLDetId det) { +int BTLElectronicsMapping::FEBoard(BTLDetId det) const { uint32_t dmodule = det.dmodule(); return BTLElectronicsMapping::FEBoardFromDM(dmodule); } -int BTLElectronicsMapping::FEBoard(uint32_t rawID) { +int BTLElectronicsMapping::FEBoard(uint32_t rawID) const { BTLDetId theId(rawID); return BTLElectronicsMapping::FEBoard(theId); } /** Returns CC board number */ -int BTLElectronicsMapping::CCBoardFromRU(uint32_t runit) { return runit; } +int BTLElectronicsMapping::CCBoardFromRU(uint32_t runit) const { return runit; } -int BTLElectronicsMapping::CCBoard(BTLDetId det) { +int BTLElectronicsMapping::CCBoard(BTLDetId det) const { uint32_t runit = det.runit(); return BTLElectronicsMapping::CCBoardFromRU(runit); } -int BTLElectronicsMapping::CCBoard(uint32_t rawID) { +int BTLElectronicsMapping::CCBoard(uint32_t rawID) const { BTLDetId theId(rawID); return BTLElectronicsMapping::CCBoard(theId); } + + + +/** TOFHIR/SM <-> e-link mapping **/ +int BTLElectronicsMapping::elinkFromSM(uint32_t dmodule, uint32_t smodCopy, int lpgbt_id) const { + + if (int(dmodule) < 0 || dmodule > BTLDetId::kDModulesPerRU){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::elinkFromSM: " + << "****************** dmodule = " << dmodule + << " not valid!"; + return -1; + } + + if (int(smodCopy) < 0 || smodCopy > BTLDetId::kSModulesPerDM){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::elinkFromSM: " + << "****************** smodCopy = " << smodCopy + << " not valid!"; + return -1; + } + + if (lpgbt_id < 0 || lpgbt_id > 1){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::hslinkFromRU: " + << "****************** lpgbt_id = " << lpgbt_id + << " not valid!"; + return -1; + } + + // from DM and chipId of the SM --> get elink + int chipId = TOFHIRASIC(dmodule, smodCopy); + return (lpgbt_id == 0) ? BTLElectronicsMapping::FE_to_ELINK_mapping_L0[dmodule][chipId] : BTLElectronicsMapping::FE_to_ELINK_mapping_L1[dmodule][chipId]; +} + +int BTLElectronicsMapping::elink(BTLDetId det, int lpgbt_id) const { + uint32_t dmodule = det.dmodule(); + uint32_t smodCopy = det.smodule(); + return BTLElectronicsMapping::elinkFromSM(dmodule, smodCopy, lpgbt_id); +} + +int BTLElectronicsMapping::elink(uint32_t rawID, int lpgbt_id) const { + BTLDetId theId(rawID); + return BTLElectronicsMapping::elink(theId, lpgbt_id); +} + +std::pair BTLElectronicsMapping::elinkToSM(int elink, int lpgbt_id) const { + + if (elink < 0 || elink > int(BTLDetId::kModulesPerRUV2)){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::elinkToSM: " + << "****************** elink = " << elink + << " not valid!"; + return std::make_pair(-1,-1); + } + + if (lpgbt_id < 0 || lpgbt_id > 1){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::elinkToSM: " + << "****************** lpgbt_id = " << lpgbt_id + << " not valid!"; + return std::make_pair(-1,-1); + } + + const auto& mapping = (lpgbt_id == 0) ? BTLElectronicsMapping::ELINK_to_FE_mapping_L0 : BTLElectronicsMapping::ELINK_to_FE_mapping_L1; + int dm = mapping[elink].first; + int chipId = mapping[elink].second; + int smCopy = chipId; + if (dm % BTLDetId::kSModulesInDM != 0){ + smCopy = BTLDetId::kSModulesInDM - chipId - 1; + } + return ( std::make_pair(dm, smCopy)); +} + + + +int BTLElectronicsMapping::hslinkToRU(int hslink) const { + return ( OptTx_map[hslink]/2 ); +} + +int BTLElectronicsMapping::hslinkFromRU(uint32_t runit, uint32_t tray, int lpgbt_id) const { + + if (int (runit) < 0 || runit > BTLDetId::kRUPerRod){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::hslinkFromRU " + << "****************** runit = " << runit + << " not valid!"; + return -1; + } + + if (lpgbt_id < 0 || lpgbt_id > 1){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::hslinkFromRU: " + << "****************** lpgbt_id = " << lpgbt_id + << " not valid!"; + return -1; + } + + const int optTxCh = 2 * runit + lpgbt_id; + // TEMPORARY MAPPING: within a group of 6 trays ( = supertray): tray 0 --> first block of 12 links, tray 1--> second block of 12 links, etc. + // For the first block (N5), channel ids of the optical tx are reversed. + // pos is the position in the tx array + const int pos = (tray%6 == 0) ? tx_inv_n5[optTxCh] : tx_inv_common[optTxCh]; + + return ( kOffsetHSLinks + 12 * (tray % 6) + pos ); +} + + +int BTLElectronicsMapping::hslink(BTLDetId det, int lpgbt_id) const { + uint32_t ru = det.runit(); + uint32_t tray = det.mtdRR(); + return BTLElectronicsMapping::hslinkFromRU(ru, tray, lpgbt_id); +} + +int BTLElectronicsMapping::hslink(uint32_t rawID, int lpgbt_id) const { + BTLDetId theId(rawID); + return BTLElectronicsMapping::hslink(theId, lpgbt_id); +} + +int BTLElectronicsMapping::SlinkFromTray(uint32_t tray, uint32_t zside) const { + + if ( int(tray) < 0 || tray >= BTLDetId::HALF_ROD){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::SlinkFromTray: " + << "****************** tray = " << tray + << " not valid!"; + return -1; + } + + if (int(zside) < 0 || zside >= 1){ + edm::LogWarning("MTDGeom") << "BTLNumberingScheme::SlinkFromTray " + << "****************** zside = " << zside + << " not valid (should be 0 or 1)!"; + return -1; + } + + // TEMPORARY MAPPING: + // trays [0-35], Z- --> Slinks [0,5] + // trays [0-35], Z+ --> Slinks [6,11] + return (MIN_SLINK_ID + tray/6 + 6 * zside); +} + +int BTLElectronicsMapping::Slink(BTLDetId det) const { + uint32_t tray = det.mtdRR(); + uint32_t zside = det.mtdSide(); + return BTLElectronicsMapping::SlinkFromTray(tray, zside); +} + +int BTLElectronicsMapping::Slink(uint32_t rawID) const { + BTLDetId theId(rawID); + return BTLElectronicsMapping::Slink(theId); +} + + +std::pair BTLElectronicsMapping::getTrayFromLinks(int slink, int hslink) const{ + + int superTray = slink - MIN_SLINK_ID; + + uint32_t zside = (superTray < 6 ) ? 0 : 1; + + int hslinkBlock = int(hslink - kOffsetHSLinks)/12; + + uint32_t tray = (superTray - 6 * zside) + 6 * hslinkBlock; + + return( std::make_pair(tray, zside)); +} diff --git a/CondFormats/MTDObjects/test/BuildFile.xml b/CondFormats/MTDObjects/test/BuildFile.xml new file mode 100644 index 0000000000000..91f0091b24e10 --- /dev/null +++ b/CondFormats/MTDObjects/test/BuildFile.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc b/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc new file mode 100644 index 0000000000000..ad37aefefb9ca --- /dev/null +++ b/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc @@ -0,0 +1,185 @@ +#include +#include +#include +#include +#include +#include + +#include "FWCore/Framework/interface/Frameworkfwd.h" +#include "FWCore/Framework/interface/one/EDAnalyzer.h" +#include "FWCore/Framework/interface/Event.h" +#include "FWCore/Framework/interface/EventSetup.h" +#include "FWCore/Framework/interface/ESTransientHandle.h" +#include "FWCore/Framework/interface/MakerMacros.h" +#include "FWCore/ParameterSet/interface/ParameterSet.h" +#include "FWCore/Utilities/interface/Exception.h" +#include "FWCore/Framework/interface/ConsumesCollector.h" + +#include "Geometry/Records/interface/IdealGeometryRecord.h" +#include "Geometry/Records/interface/DDSpecParRegistryRcd.h" + +#include "DetectorDescription/DDCMS/interface/DDDetector.h" +#include "DetectorDescription/DDCMS/interface/DDSolidShapes.h" +#include "DetectorDescription/DDCMS/interface/DDFilteredView.h" +#include "DetectorDescription/DDCMS/interface/DDSpecParRegistry.h" + +#include "Geometry/MTDCommonData/interface/MTDBaseNumber.h" +#include "Geometry/MTDCommonData/interface/BTLNumberingScheme.h" +//#include "Geometry/MTDCommonData/interface/BTLElectronicsMapping.h" +#include "Geometry/MTDCommonData/interface/MTDTopologyMode.h" + +#include "Geometry/MTDGeometryBuilder/interface/MTDTopology.h" +#include "Geometry/Records/interface/MTDTopologyRcd.h" + +#include "DataFormats/ForwardDetId/interface/BTLDetId.h" + +#include "CondFormats/MTDObjects/interface/BTLElectronicsMapping.h" + +#include "DataFormats/Math/interface/angle_units.h" +#include "DataFormats/Math/interface/Rounding.h" +#include + +using namespace cms; + +class TestBTLElectronicsMapping : public edm::one::EDAnalyzer<> { +public: + explicit TestBTLElectronicsMapping(const edm::ParameterSet&); + ~TestBTLElectronicsMapping() override = default; + + void beginJob() override {} + void analyze(edm::Event const&, edm::EventSetup const&) override; + void endJob() override {} + + void theBaseNumber(cms::DDFilteredView& fv); + +private: + const edm::ESInputTag tag_; + std::string ddTopNodeName_; + + MTDBaseNumber thisN_; + BTLNumberingScheme btlNS_; + + edm::ESGetToken mtdtopoToken_; + edm::ESGetToken dddetToken_; + edm::ESGetToken dspecToken_; +}; + + +TestBTLElectronicsMapping::TestBTLElectronicsMapping(const edm::ParameterSet& iConfig) + : tag_(iConfig.getParameter("DDDetector")), + ddTopNodeName_(iConfig.getUntrackedParameter("ddTopNodeName", "BarrelTimingLayer")), + thisN_(), + btlNS_(){ + mtdtopoToken_ = esConsumes(); + dddetToken_ = esConsumes(tag_); + dspecToken_ = esConsumes(tag_); +} + +void TestBTLElectronicsMapping::analyze(const edm::Event& iEvent, const edm::EventSetup& iSetup) { + + auto pDD = iSetup.getTransientHandle(dddetToken_); + + auto pSP = iSetup.getTransientHandle(dspecToken_); + + auto topologyHandle = iSetup.getTransientHandle(mtdtopoToken_); + const MTDTopology* topology = topologyHandle.product(); + auto btlCrysLayout = MTDTopologyMode::crysLayoutFromTopoMode(topology->getMTDTopologyMode()); + + if (ddTopNodeName_ != "BarrelTimingLayer") { + edm::LogWarning("TestBTLElectronicsMapping") << ddTopNodeName_ << "Not valid top BarrelTimingLayer volume"; + return; + } + + DDFilteredView fv(pDD.product(), pDD.product()->description()->worldVolume()); + fv.next(0); + edm::LogInfo("TestBTLElectronicsMapping") << fv.name(); + + DDSpecParRefs specs; + pSP.product()->filter(specs, "ReadOutName", "FastTimerHitsBarrel"); + + bool insideBTL = false; + uint32_t startLevel = 0; + + do { + + if (dd4hep::dd::noNamespace(fv.name()) == "BarrelTimingLayer") { + insideBTL = true; + startLevel = fv.navPos().size(); + edm::LogInfo("TestBTLElectronicsMapping") << "insideBTL = " << insideBTL; + if (static_cast(btlCrysLayout) < static_cast(BTLDetId::CrysLayout::v4)) { + edm::LogInfo("DD4hep_TestMTDIdealGeometry") + << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) + << ", use layout 7 (v4) or later!" << std::endl; + } + continue; + } + + if (insideBTL && fv.navPos().size() < startLevel) { + break; // exited BTL --> break loop + } + + if (!insideBTL) continue; + + std::stringstream ss; + + theBaseNumber(fv); + + bool isSens = false; + + for (auto const& t : specs) { + for (auto const& it : t.second->paths) { + if (dd4hep::dd::compareEqual(dd4hep::dd::noNamespace(fv.name()), dd4hep::dd::realTopName(it))) { + isSens = true; + break; + } + } + } + + if (isSens) { + + std::stringstream sunitt; + std::stringstream snum; + + BTLDetId theId(btlNS_.getUnitID(thisN_)); + sunitt << theId.rawId(); + snum << theId; + + if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { + BTLElectronicsMapping btlElMap = BTLElectronicsMapping(btlCrysLayout); + snum << "\n"; + snum << "----------------------------------------------------------------------------" << std::endl; + snum << " CCBoard: " << btlElMap.CCBoard(theId) << " FEBoard: " << btlElMap.FEBoard(theId) + << " TOFHIRASIC: " << btlElMap.TOFHIRASIC(theId) << "\n SiPMCh minus: " << btlElMap.SiPMCh(theId, 0) + << " plus: " << btlElMap.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlElMap.TOFHIRCh(theId, 0) + << " plus: " << btlElMap.TOFHIRCh(theId, 1) << "\n"; + snum << "\n"; + snum << " DM, SM, chipId : " << theId.dmodule() << ", " << theId.smodule() << ", " << btlElMap.TOFHIRASIC(theId) << " e-link: " << btlElMap.elink(theId) << "\n" + << " DM, SM from e-link: " << btlElMap.elinkToSM(btlElMap.elink(theId)).first << ", " << btlElMap.elinkToSM(btlElMap.elink(theId)).second << "\n"; + snum << "\n"; + snum << " Tray: " << theId.mtdRR() << " RU: " << theId.runit()<< " hs-link : " << btlElMap.hslink(theId) << "\n" + << " RU from hs-link: " << btlElMap.hslinkToRU( btlElMap.hslink(theId) ) << "\n"; + snum << "\n"; + snum << " Tray, side : " << theId.mtdRR() << ", " << theId.mtdSide() << " S-link : " << btlElMap.Slink(theId) << "\n" + << " Tray, side from S-link, HS-link: " << btlElMap.getTrayFromLinks(btlElMap.Slink(theId),btlElMap.hslink(theId)).first << ", " << btlElMap.getTrayFromLinks(btlElMap.Slink(theId),btlElMap.hslink(theId)).second << "\n"; + snum << "----------------------------------------------------------------------------" << std::endl; + } + edm::LogInfo("TestBTLElectronicsMapping") << snum.str(); + } + } while (fv.next(0)); +} + +void TestBTLElectronicsMapping::theBaseNumber(cms::DDFilteredView& fv) { + thisN_.reset(); + thisN_.setSize(fv.navPos().size()); + + for (uint ii = 0; ii < fv.navPos().size(); ii++) { + std::string_view name((fv.geoHistory()[ii])->GetName()); + size_t ipos = name.rfind('_'); + thisN_.addLevel(name.substr(0, ipos), fv.copyNos()[ii]); +#ifdef EDM_ML_DEBUG + edm::LogVerbatim("TestBTLElectronicsMapping") << ii << " " << name.substr(0, ipos) << " " << fv.copyNos()[ii]; +#endif + } +} + +DEFINE_FWK_MODULE(TestBTLElectronicsMapping); diff --git a/CondFormats/MTDObjects/test/testBTLElectronicsMapping.py b/CondFormats/MTDObjects/test/testBTLElectronicsMapping.py new file mode 100644 index 0000000000000..33fcb7a5d7213 --- /dev/null +++ b/CondFormats/MTDObjects/test/testBTLElectronicsMapping.py @@ -0,0 +1,41 @@ +import FWCore.ParameterSet.Config as cms + +import Configuration.Geometry.defaultPhase2ConditionsEra_cff as _settings +import Geometry.MTDCommonData.defaultMTDConditionsEra_cff as _mtdgeo +_mtdgeo.check_mtdgeo() +_PH2_GLOBAL_TAG, _PH2_ERA = _settings.get_era_and_conditions(_mtdgeo.MTD_DEFAULT_VERSION) +from Configuration.ProcessModifiers.dd4hep_cff import dd4hep + +process = cms.Process("CompareGeometryTest",_PH2_ERA,dd4hep) + +process.source = cms.Source("EmptySource") + +process.maxEvents = cms.untracked.PSet( + input = cms.untracked.int32(1) + ) + +process.load("FWCore.MessageLogger.MessageLogger_cfi") +process.MessageLogger.cerr.threshold = cms.untracked.string('INFO') +process.MessageLogger.cerr.INFO = cms.untracked.PSet( + #limit = cms.untracked.int32(0) + limit = cms.untracked.int32(-1) +) +process.MessageLogger.cerr.TestBTLElectronicsMapping = cms.untracked.PSet( + limit = cms.untracked.int32(-1) + #limit = cms.untracked.int32(0) +) + + +process.load("Geometry.MTDNumberingBuilder.mtdTopology_cfi") + +process.load('Geometry.MTDCommonData.GeometryDD4hepExtendedRun4MTDDefaultReco_cff') + +process.testBTL = cms.EDAnalyzer("TestBTLElectronicsMapping", + DDDetector = cms.ESInputTag('',''), + ddTopNodeName = cms.untracked.string('BarrelTimingLayer') + ) + +process.Timing = cms.Service("Timing") + +process.p1 = cms.Path(process.testBTL) + diff --git a/Geometry/MTDCommonData/interface/BTLElectronicsMapping.h b/Geometry/MTDCommonData/interface/BTLElectronicsMapping.h deleted file mode 100644 index e0f24781b67d1..0000000000000 --- a/Geometry/MTDCommonData/interface/BTLElectronicsMapping.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef DATAFORMATS_BTLELECTRONICSMAPPING_H -#define DATAFORMATS_BTLELECTRONICSMAPPING_H 1 - -#include -#include - -#include "DataFormats/ForwardDetId/interface/BTLDetId.h" -#include - -/** \brief BTL TOFHIR channel mapping with crystal BTLDetId - Convention: - SiPMside 0 == Minus Side - SiPMside 1 == Plus Side - */ - -class BTLElectronicsMapping { -public: - struct SiPMChPair { - int Minus; - int Plus; - }; - - struct TOFHIRChPair { - int Minus; - int Plus; - }; - - // Map SiPM Channel to crystal bars for Forward module orientation - static constexpr std::array SiPMChannelMapFW{ - {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, - 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0}}; - // Map SiPM Channel to crystal bars for Backward module orientation - static constexpr std::array SiPMChannelMapBW{ - {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, - 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16}}; - - // Map TOFHIR Channel to SiPM Channel - static constexpr std::array THChannelMap{ - {4, 1, 0, 3, 2, 6, 7, 9, 5, 11, 8, 12, 10, 14, 15, 13, - 17, 16, 18, 19, 20, 23, 21, 26, 22, 27, 28, 31, 30, 24, 25, 29}}; - - /** Default constructor -- invalid value */ - BTLElectronicsMapping(const BTLDetId::CrysLayout lay); - - // Get SiPM Channel number from crystal - int SiPMCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide); - int SiPMCh(BTLDetId det, uint32_t SiPMSide); - int SiPMCh(uint32_t rawID, uint32_t SiPMSide); - - SiPMChPair GetSiPMChPair(uint32_t smodCopy, uint32_t crystal); - SiPMChPair GetSiPMChPair(BTLDetId det); - SiPMChPair GetSiPMChPair(uint32_t rawID); - - // Get TOFHIR Channel number from crystal - int TOFHIRCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide); - int TOFHIRCh(BTLDetId det, uint32_t SiPMSide); - int TOFHIRCh(uint32_t rawID, uint32_t SiPMSide); - - TOFHIRChPair GetTOFHIRChPair(uint32_t smodCopy, uint32_t crystal); - TOFHIRChPair GetTOFHIRChPair(BTLDetId det); - TOFHIRChPair GetTOFHIRChPair(uint32_t rawID); - - // Get xtal from TOFHIR Channel number - int THChToXtal(uint32_t smodCopy, uint32_t THCh); - BTLDetId THChToBTLDetId( - uint32_t zside, uint32_t rod, uint32_t runit, uint32_t dmodule, uint32_t smodCopy, uint32_t THCh); - - /** Returns TOFHIR ASIC number in construction database. */ - int TOFHIRASIC(uint32_t dmodule, uint32_t smodCopy); - int TOFHIRASIC(BTLDetId det); - int TOFHIRASIC(uint32_t rawID); - - /** Returns FE board number */ - int FEBoardFromDM(uint32_t dmodule); - int FEBoard(BTLDetId det); - int FEBoard(uint32_t rawID); - - /** Returns CC board number */ - int CCBoardFromRU(uint32_t dmodule); - int CCBoard(BTLDetId det); - int CCBoard(uint32_t rawID); - -private: -}; - -#endif diff --git a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc index 6fd60e327c67d..0202844198add 100644 --- a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc +++ b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc @@ -26,7 +26,7 @@ #include "Geometry/MTDCommonData/interface/MTDBaseNumber.h" #include "Geometry/MTDCommonData/interface/BTLNumberingScheme.h" #include "Geometry/MTDCommonData/interface/ETLNumberingScheme.h" -#include "Geometry/MTDCommonData/interface/BTLElectronicsMapping.h" +//#include "Geometry/MTDCommonData/interface/BTLElectronicsMapping.h" #include "Geometry/MTDCommonData/interface/MTDTopologyMode.h" #include "Geometry/MTDGeometryBuilder/interface/MTDTopology.h" @@ -154,9 +154,9 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E isBarrel = true; edm::LogInfo("DD4hep_TestMTDIdealGeometry") << "isBarrel = " << isBarrel; if (static_cast(btlCrysLayout) < static_cast(BTLDetId::CrysLayout::v4)) { - edm::LogInfo("DD4hep_TestMTDIdealGeometry") - << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) - << ", use layout 7 (v4) or later!" << std::endl; + //edm::LogInfo("DD4hep_TestMTDIdealGeometry") + // << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) + // << ", use layout 7 (v4) or later!" << std::endl; } } else if (dd4hep::dd::noNamespace(fv.name()) == "EndcapTimingLayer") { isBarrel = false; @@ -235,7 +235,8 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E sunitt << theId.rawId(); snum << theId; - if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { + /* + if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { BTLElectronicsMapping btlEM = BTLElectronicsMapping(btlCrysLayout); snum << "\n"; snum << "----------------------------------------------------------------------------" << std::endl; @@ -244,8 +245,9 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E << " plus: " << btlEM.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlEM.TOFHIRCh(theId, 0) << " plus: " << btlEM.TOFHIRCh(theId, 1) << "\n"; snum << "----------------------------------------------------------------------------" << std::endl; - } - } else { + } + */ + } else { ETLDetId theId(etlNS_.getUnitID(thisN_)); sunitt << theId.rawId(); snum << theId; From fcf205aef8384e0f065a1f486a74bbe62c420e1e Mon Sep 17 00:00:00 2001 From: Martina Date: Mon, 11 May 2026 12:44:24 +0200 Subject: [PATCH 2/9] bug fix --- CondFormats/MTDObjects/src/BTLElectronicsMapping.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc b/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc index ef881f2993c2f..36209cd0b314e 100644 --- a/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc +++ b/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc @@ -338,7 +338,7 @@ int BTLElectronicsMapping::SlinkFromTray(uint32_t tray, uint32_t zside) const { return -1; } - if (int(zside) < 0 || zside >= 1){ + if (int(zside) < 0 || zside > 1){ edm::LogWarning("MTDGeom") << "BTLNumberingScheme::SlinkFromTray " << "****************** zside = " << zside << " not valid (should be 0 or 1)!"; @@ -371,7 +371,7 @@ std::pair BTLElectronicsMapping::getTrayFromLinks(int slink, int hslinkBlock = int(hslink - kOffsetHSLinks)/12; - uint32_t tray = (superTray - 6 * zside) + 6 * hslinkBlock; + uint32_t tray = (superTray - 6 * zside) * 6 + hslinkBlock; return( std::make_pair(tray, zside)); } From 47a9607812ec97b4f170dee5f4e956601754d20c Mon Sep 17 00:00:00 2001 From: Martina Date: Mon, 11 May 2026 12:50:00 +0200 Subject: [PATCH 3/9] restore testing in Geometry/MTDCommonData --- Geometry/MTDCommonData/test/BuildFile.xml | 1 + .../test/DD4hep_TestMTDIdealGeometry.cc | 14 +++++++------- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/Geometry/MTDCommonData/test/BuildFile.xml b/Geometry/MTDCommonData/test/BuildFile.xml index 25ec6655161e5..d0b6df1c9244c 100644 --- a/Geometry/MTDCommonData/test/BuildFile.xml +++ b/Geometry/MTDCommonData/test/BuildFile.xml @@ -20,6 +20,7 @@ + diff --git a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc index 0202844198add..46d14108ea8b3 100644 --- a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc +++ b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc @@ -35,6 +35,8 @@ #include "DataFormats/ForwardDetId/interface/BTLDetId.h" #include "DataFormats/ForwardDetId/interface/ETLDetId.h" +#include "CondFormats/MTDObjects/interface/BTLElectronicsMapping.h" + #include "DataFormats/Math/interface/angle_units.h" #include "DataFormats/Math/interface/Rounding.h" #include @@ -154,9 +156,9 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E isBarrel = true; edm::LogInfo("DD4hep_TestMTDIdealGeometry") << "isBarrel = " << isBarrel; if (static_cast(btlCrysLayout) < static_cast(BTLDetId::CrysLayout::v4)) { - //edm::LogInfo("DD4hep_TestMTDIdealGeometry") - // << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) - // << ", use layout 7 (v4) or later!" << std::endl; + edm::LogInfo("DD4hep_TestMTDIdealGeometry") + << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) + << ", use layout 7 (v4) or later!" << std::endl; } } else if (dd4hep::dd::noNamespace(fv.name()) == "EndcapTimingLayer") { isBarrel = false; @@ -235,8 +237,7 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E sunitt << theId.rawId(); snum << theId; - /* - if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { + if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { BTLElectronicsMapping btlEM = BTLElectronicsMapping(btlCrysLayout); snum << "\n"; snum << "----------------------------------------------------------------------------" << std::endl; @@ -245,8 +246,7 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E << " plus: " << btlEM.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlEM.TOFHIRCh(theId, 0) << " plus: " << btlEM.TOFHIRCh(theId, 1) << "\n"; snum << "----------------------------------------------------------------------------" << std::endl; - } - */ + } } else { ETLDetId theId(etlNS_.getUnitID(thisN_)); sunitt << theId.rawId(); From 2a6fb71f7a6e4f59e6b2b323f906c79cb9bd0093 Mon Sep 17 00:00:00 2001 From: Martina Date: Mon, 11 May 2026 12:57:00 +0200 Subject: [PATCH 4/9] code-format --- .../interface/BTLElectronicsMapping.h | 137 ++++++------------ .../MTDObjects/src/BTLElectronicsMapping.cc | 104 ++++++------- .../test/TestBTLElectronicsMapping.cc | 89 ++++++------ .../test/DD4hep_TestMTDIdealGeometry.cc | 10 +- 4 files changed, 141 insertions(+), 199 deletions(-) diff --git a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h index 1d79b3751555e..f7cde23324582 100644 --- a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h +++ b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h @@ -80,91 +80,51 @@ class BTLElectronicsMapping { int CCBoard(BTLDetId det) const; int CCBoard(uint32_t rawID) const; - /** ======== DAQ cabling mapping ========== **/ /** E-LINK <-> TOFHIR/SM **/ - /** HS-link <-> CC/RU to Serenity **/ + /** HS-link <-> CC/RU to Serenity **/ /** S-link <-> FED Id (6 trays) **/ /** ======================================= **/ - + /** E-LINK **/ /** E-LINK identifies which TOFHIR/SM within a CC. The mapping depends if lpgbt L0 or L1 is used. Default is L0. **/ /** Ref: https://gitlab.cern.ch/btl-commissioning/mtd_daq/-/blob/tif_new_s1p2/src/mtd_daq/configurator/mappings.py?ref_type=heads#L79-130 */ - - static constexpr std::array, BTLDetId::kDModulesPerRU*2 > ELINK_to_FE_mapping_L0{ - {{7, 1}, // e-link 0: {DM 7, chipId 1} - {7, 0}, // e-link 1: {DM 7, chipId 0} - {3, 1}, - {3, 0}, - {2, 1}, - {2, 0}, - {0, 0}, - {0, 1}, - {1, 1}, - {1, 0}, - {5, 0}, - {5, 1}, - {4, 1}, - {4, 0}, - {8, 0}, - {9, 1}, - {9, 0}, - {8, 1}, - {10, 0}, - {10, 1}, - {11, 1}, - {11, 0}, - {6, 1}, - {6, 0} // e-link 23: {DM 6, chipId 0} - }}; - - static constexpr std::array, BTLDetId::kDModulesPerRU*2> ELINK_to_FE_mapping_L1{ - {{6, 1}, // e-link 0: {DM 6, chipId 1} - {3, 1}, // e-link 1: {DM 3, chipId 1} - {11, 0}, - {11, 1}, - {3, 0}, - {6, 0}, - {2, 1}, - {2, 0}, - {1, 0}, - {1, 1}, - {0, 0}, - {0, 1}, - {5, 1}, - {5, 0}, - {4, 0}, - {4, 1}, - {9, 1}, - {9, 0}, - {8, 0}, - {8, 1}, - {10, 0}, - {10, 1}, - {11, 0}, - {11, 1} // e-link 23: {DM 11, chipId 1} - }}; + + static constexpr std::array, BTLDetId::kDModulesPerRU * 2> ELINK_to_FE_mapping_L0{{ + {7, 1}, // e-link 0: {DM 7, chipId 1} + {7, 0}, // e-link 1: {DM 7, chipId 0} + {3, 1}, {3, 0}, {2, 1}, {2, 0}, {0, 0}, {0, 1}, {1, 1}, {1, 0}, {5, 0}, {5, 1}, {4, 1}, {4, 0}, + {8, 0}, {9, 1}, {9, 0}, {8, 1}, {10, 0}, {10, 1}, {11, 1}, {11, 0}, {6, 1}, {6, 0} // e-link 23: {DM 6, chipId 0} + }}; + + static constexpr std::array, BTLDetId::kDModulesPerRU * 2> ELINK_to_FE_mapping_L1{{ + {6, 1}, // e-link 0: {DM 6, chipId 1} + {3, 1}, // e-link 1: {DM 3, chipId 1} + {11, 0}, {11, 1}, {3, 0}, {6, 0}, {2, 1}, {2, 0}, {1, 0}, {1, 1}, {0, 0}, {0, 1}, {5, 1}, {5, 0}, + {4, 0}, {4, 1}, {9, 1}, {9, 0}, {8, 0}, {8, 1}, {10, 0}, {10, 1}, {11, 0}, {11, 1} // e-link 23: {DM 11, chipId 1} + }}; // ELINK Reverse mapping: given an FE/DM (0-11) and a ChipId (0-1), find the corresponding e-link static constexpr auto buildFEtoElinkMapping = [](auto const& mapping) { - std::array, BTLDetId::kDModulesPerRU > tmp {}; // pair is (DM, chipId), there are 12 pairs. - for (auto& row : tmp) row.fill(-1);// initialize to -1 - for (unsigned int elink = 0; elink < BTLDetId::kDModulesPerRU*2; ++elink) { + std::array, BTLDetId::kDModulesPerRU> tmp{}; // pair is (DM, chipId), there are 12 pairs. + for (auto& row : tmp) + row.fill(-1); // initialize to -1 + for (unsigned int elink = 0; elink < BTLDetId::kDModulesPerRU * 2; ++elink) { tmp[mapping[elink].first][mapping[elink].second] = static_cast(elink); } return tmp; }; - + static constexpr auto FE_to_ELINK_mapping_L0 = buildFEtoElinkMapping(ELINK_to_FE_mapping_L0); static constexpr auto FE_to_ELINK_mapping_L1 = buildFEtoElinkMapping(ELINK_to_FE_mapping_L1); - - // -- Get the e-link for a given SM - int elinkFromSM(uint32_t dmodule, uint32_t smodCopy, int lpgbt_id = 0) const; // e-link from DM and SM - int elink(BTLDetId det, int lpgbt_id = 0) const; // e-link from BTLDetId - int elink(uint32_t rawID, int lpgbt_id = 0) const; // e-link from rawID + + // -- Get the e-link for a given SM + int elinkFromSM(uint32_t dmodule, uint32_t smodCopy, int lpgbt_id = 0) const; // e-link from DM and SM + int elink(BTLDetId det, int lpgbt_id = 0) const; // e-link from BTLDetId + int elink(uint32_t rawID, int lpgbt_id = 0) const; // e-link from rawID // -- Get the (DM,SM) for a given e-link std::pair elinkToSM(int elink, int lpgbt_id = 0) const; - + // ** HS-LINK **/ // ** HS-link = link CC/RU to Serenity **/ // Mapping of FPGA Tx port number (hs-link) to optical Tx channels provided by O. Sahin. @@ -173,10 +133,10 @@ class BTLElectronicsMapping { // Within each block: // Opt Tx 0, 2, 4, 6, 8, 10 --> correspond to CC 0,1,2,3,4,5 for LPGBT0 // Opt Tx 1, 3, 5, 7, 9, 11 --> correspond to CC 0,1,2,3,4,5 for LPGBT1 - // !!!! Which tray goes to which block for now is arbitrary, but for the fact that 6 trays are contiguos + // !!!! Which tray goes to which block for now is arbitrary, but for the fact that 6 trays are contiguos // TEMPORARY MAPPING: within a group of 6 trays ( = supertray): tray 0 --> first block of 12 links, tray 1--> second block of 12 links, etc. - // For the first block (FF_N5), channel ids of the optical tx are reversed. - + // For the first block (FF_N5), channel ids of the optical tx are reversed. + /* struct Tx { const char* name; int index; @@ -271,40 +231,40 @@ class BTLElectronicsMapping { }}; */ - - static constexpr uint32_t kNumHSLinks = 72; // number of HS links: in each Serenity 6 trays x 12 links - static constexpr uint32_t kOffsetHSLinks = 4; // offset (HS link Ids start from 4 (0-3 reserved) - static constexpr uint32_t MIN_SLINK_ID = 1000; // arbitrary for now - + static constexpr uint32_t kNumHSLinks = 72; // number of HS links: in each Serenity 6 trays x 12 links + static constexpr uint32_t kOffsetHSLinks = 4; // offset (HS link Ids start from 4 (0-3 reserved) + static constexpr uint32_t MIN_SLINK_ID = 1000; // arbitrary for now + // Define an array of 12 elements, each element is the optical Tx channel Id (this depends on the FF). Then each channel will map to a CC/RU - static constexpr std::array optTxCh_n5 = { 1, 3, 5, 0, 2, 4, 6, 8, 10, 7, 9, 11}; // 12 = 6 RUs x 2 LPGBTs - static constexpr std::array optTxCh_common = { 11, 9, 7, 10, 8, 6, 4, 2, 0, 5, 3, 1};// 12 = 6 RUs x 2 LPGBTs + static constexpr std::array optTxCh_n5 = { + 1, 3, 5, 0, 2, 4, 6, 8, 10, 7, 9, 11}; // 12 = 6 RUs x 2 LPGBTs + static constexpr std::array optTxCh_common = { + 11, 9, 7, 10, 8, 6, 4, 2, 0, 5, 3, 1}; // 12 = 6 RUs x 2 LPGBTs static constexpr auto OptTx_map = []() { std::array tmp; tmp.fill(-1); for (unsigned int i = 0; i < kNumHSLinks / 12; i++) { for (int j = 0; j < 12; j++) { - int hslink_id = kOffsetHSLinks + i * 12 + j; - tmp[hslink_id] = (i == 0) ? optTxCh_n5[j] : optTxCh_common[j]; + int hslink_id = kOffsetHSLinks + i * 12 + j; + tmp[hslink_id] = (i == 0) ? optTxCh_n5[j] : optTxCh_common[j]; } } return tmp; - }(); + }(); - // Build inverse mapping static constexpr auto tx_to_index = [](const std::array& p) { std::array inv{}; inv.fill(-1); for (int i = 0; i < 12; ++i) - inv[p[i]] = i; + inv[p[i]] = i; return inv; }; static constexpr auto tx_inv_n5 = tx_to_index(optTxCh_n5); static constexpr auto tx_inv_common = tx_to_index(optTxCh_common); - + // -- Get the CC/RU corresponding to a given HS-link int hslinkToRU(int hslink) const; // -- Get the HS-link corresponding to a given RU/CC in a tray @@ -312,21 +272,20 @@ class BTLElectronicsMapping { int hslink(BTLDetId det, int lpgbt_id = 0) const; int hslink(uint32_t rawID, int lpgbt_id = 0) const; - /** S-link **/ /** one S-link corresponds to a group of 6 trays. one S-link = one FEDId **/ /** !!!!! TEMPORARY mapping for now until FEDId not assigned !!!!! **/ // TEMPORARY MAPPING: // trays [0-35], z- --> Slinks [0,5] // trays [0-35], z+ --> Slinks [6,11] - - // -- Get the tray Id from combination of S-link (--> group fo 6 trays) and HS-link (which tray in that S-link, i.e. - std::pair getTrayFromLinks(int slink, int hslink) const; // return tray number [0-35] and z side [0,1] given S-link and HS-link Id + + // -- Get the tray Id from combination of S-link (--> group fo 6 trays) and HS-link (which tray in that S-link, i.e. + std::pair getTrayFromLinks( + int slink, int hslink) const; // return tray number [0-35] and z side [0,1] given S-link and HS-link Id // -- Get the S-link for a given tray - int SlinkFromTray(uint32_t tray, uint32_t zside) const; + int SlinkFromTray(uint32_t tray, uint32_t zside) const; int Slink(BTLDetId det) const; int Slink(uint32_t rawID) const; - private: }; diff --git a/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc b/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc index 36209cd0b314e..c081b5844e7af 100644 --- a/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc +++ b/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc @@ -17,7 +17,7 @@ BTLElectronicsMapping::BTLElectronicsMapping(const BTLDetId::CrysLayout lay) { // Get SiPM Channel from crystal ID -int BTLElectronicsMapping::SiPMCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide) const{ +int BTLElectronicsMapping::SiPMCh(uint32_t smodCopy, uint32_t crystal, uint32_t SiPMSide) const { if (0 > int(crystal) || crystal > BTLDetId::kCrystalsPerModuleV2) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::BTLElectronicsMapping(): " << "****************** Bad crystal number = " << int(crystal); @@ -218,35 +218,30 @@ int BTLElectronicsMapping::CCBoard(uint32_t rawID) const { return BTLElectronicsMapping::CCBoard(theId); } - - /** TOFHIR/SM <-> e-link mapping **/ int BTLElectronicsMapping::elinkFromSM(uint32_t dmodule, uint32_t smodCopy, int lpgbt_id) const { - - if (int(dmodule) < 0 || dmodule > BTLDetId::kDModulesPerRU){ + if (int(dmodule) < 0 || dmodule > BTLDetId::kDModulesPerRU) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::elinkFromSM: " - << "****************** dmodule = " << dmodule - << " not valid!"; + << "****************** dmodule = " << dmodule << " not valid!"; return -1; } - - if (int(smodCopy) < 0 || smodCopy > BTLDetId::kSModulesPerDM){ + + if (int(smodCopy) < 0 || smodCopy > BTLDetId::kSModulesPerDM) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::elinkFromSM: " - << "****************** smodCopy = " << smodCopy - << " not valid!"; + << "****************** smodCopy = " << smodCopy << " not valid!"; return -1; } - if (lpgbt_id < 0 || lpgbt_id > 1){ + if (lpgbt_id < 0 || lpgbt_id > 1) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::hslinkFromRU: " - << "****************** lpgbt_id = " << lpgbt_id - << " not valid!"; + << "****************** lpgbt_id = " << lpgbt_id << " not valid!"; return -1; } // from DM and chipId of the SM --> get elink - int chipId = TOFHIRASIC(dmodule, smodCopy); - return (lpgbt_id == 0) ? BTLElectronicsMapping::FE_to_ELINK_mapping_L0[dmodule][chipId] : BTLElectronicsMapping::FE_to_ELINK_mapping_L1[dmodule][chipId]; + int chipId = TOFHIRASIC(dmodule, smodCopy); + return (lpgbt_id == 0) ? BTLElectronicsMapping::FE_to_ELINK_mapping_L0[dmodule][chipId] + : BTLElectronicsMapping::FE_to_ELINK_mapping_L1[dmodule][chipId]; } int BTLElectronicsMapping::elink(BTLDetId det, int lpgbt_id) const { @@ -261,63 +256,53 @@ int BTLElectronicsMapping::elink(uint32_t rawID, int lpgbt_id) const { } std::pair BTLElectronicsMapping::elinkToSM(int elink, int lpgbt_id) const { - - if (elink < 0 || elink > int(BTLDetId::kModulesPerRUV2)){ + if (elink < 0 || elink > int(BTLDetId::kModulesPerRUV2)) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::elinkToSM: " - << "****************** elink = " << elink - << " not valid!"; - return std::make_pair(-1,-1); + << "****************** elink = " << elink << " not valid!"; + return std::make_pair(-1, -1); } - if (lpgbt_id < 0 || lpgbt_id > 1){ + if (lpgbt_id < 0 || lpgbt_id > 1) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::elinkToSM: " - << "****************** lpgbt_id = " << lpgbt_id - << " not valid!"; - return std::make_pair(-1,-1); + << "****************** lpgbt_id = " << lpgbt_id << " not valid!"; + return std::make_pair(-1, -1); } - const auto& mapping = (lpgbt_id == 0) ? BTLElectronicsMapping::ELINK_to_FE_mapping_L0 : BTLElectronicsMapping::ELINK_to_FE_mapping_L1; - int dm = mapping[elink].first; + const auto& mapping = + (lpgbt_id == 0) ? BTLElectronicsMapping::ELINK_to_FE_mapping_L0 : BTLElectronicsMapping::ELINK_to_FE_mapping_L1; + int dm = mapping[elink].first; int chipId = mapping[elink].second; int smCopy = chipId; - if (dm % BTLDetId::kSModulesInDM != 0){ + if (dm % BTLDetId::kSModulesInDM != 0) { smCopy = BTLDetId::kSModulesInDM - chipId - 1; } - return ( std::make_pair(dm, smCopy)); + return (std::make_pair(dm, smCopy)); } - - -int BTLElectronicsMapping::hslinkToRU(int hslink) const { - return ( OptTx_map[hslink]/2 ); -} +int BTLElectronicsMapping::hslinkToRU(int hslink) const { return (OptTx_map[hslink] / 2); } int BTLElectronicsMapping::hslinkFromRU(uint32_t runit, uint32_t tray, int lpgbt_id) const { - - if (int (runit) < 0 || runit > BTLDetId::kRUPerRod){ + if (int(runit) < 0 || runit > BTLDetId::kRUPerRod) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::hslinkFromRU " - << "****************** runit = " << runit - << " not valid!"; + << "****************** runit = " << runit << " not valid!"; return -1; } - if (lpgbt_id < 0 || lpgbt_id > 1){ + if (lpgbt_id < 0 || lpgbt_id > 1) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::hslinkFromRU: " - << "****************** lpgbt_id = " << lpgbt_id - << " not valid!"; + << "****************** lpgbt_id = " << lpgbt_id << " not valid!"; return -1; } - - const int optTxCh = 2 * runit + lpgbt_id; + + const int optTxCh = 2 * runit + lpgbt_id; // TEMPORARY MAPPING: within a group of 6 trays ( = supertray): tray 0 --> first block of 12 links, tray 1--> second block of 12 links, etc. // For the first block (N5), channel ids of the optical tx are reversed. // pos is the position in the tx array - const int pos = (tray%6 == 0) ? tx_inv_n5[optTxCh] : tx_inv_common[optTxCh]; + const int pos = (tray % 6 == 0) ? tx_inv_n5[optTxCh] : tx_inv_common[optTxCh]; - return ( kOffsetHSLinks + 12 * (tray % 6) + pos ); + return (kOffsetHSLinks + 12 * (tray % 6) + pos); } - int BTLElectronicsMapping::hslink(BTLDetId det, int lpgbt_id) const { uint32_t ru = det.runit(); uint32_t tray = det.mtdRR(); @@ -330,25 +315,22 @@ int BTLElectronicsMapping::hslink(uint32_t rawID, int lpgbt_id) const { } int BTLElectronicsMapping::SlinkFromTray(uint32_t tray, uint32_t zside) const { - - if ( int(tray) < 0 || tray >= BTLDetId::HALF_ROD){ + if (int(tray) < 0 || tray >= BTLDetId::HALF_ROD) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::SlinkFromTray: " - << "****************** tray = " << tray - << " not valid!"; + << "****************** tray = " << tray << " not valid!"; return -1; } - if (int(zside) < 0 || zside > 1){ + if (int(zside) < 0 || zside > 1) { edm::LogWarning("MTDGeom") << "BTLNumberingScheme::SlinkFromTray " - << "****************** zside = " << zside - << " not valid (should be 0 or 1)!"; + << "****************** zside = " << zside << " not valid (should be 0 or 1)!"; return -1; } - + // TEMPORARY MAPPING: // trays [0-35], Z- --> Slinks [0,5] // trays [0-35], Z+ --> Slinks [6,11] - return (MIN_SLINK_ID + tray/6 + 6 * zside); + return (MIN_SLINK_ID + tray / 6 + 6 * zside); } int BTLElectronicsMapping::Slink(BTLDetId det) const { @@ -362,16 +344,14 @@ int BTLElectronicsMapping::Slink(uint32_t rawID) const { return BTLElectronicsMapping::Slink(theId); } +std::pair BTLElectronicsMapping::getTrayFromLinks(int slink, int hslink) const { + int superTray = slink - MIN_SLINK_ID; -std::pair BTLElectronicsMapping::getTrayFromLinks(int slink, int hslink) const{ + uint32_t zside = (superTray < 6) ? 0 : 1; - int superTray = slink - MIN_SLINK_ID; + int hslinkBlock = int(hslink - kOffsetHSLinks) / 12; - uint32_t zside = (superTray < 6 ) ? 0 : 1; - - int hslinkBlock = int(hslink - kOffsetHSLinks)/12; - uint32_t tray = (superTray - 6 * zside) * 6 + hslinkBlock; - return( std::make_pair(tray, zside)); + return (std::make_pair(tray, zside)); } diff --git a/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc b/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc index ad37aefefb9ca..b765f1720e398 100644 --- a/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc +++ b/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc @@ -64,19 +64,17 @@ class TestBTLElectronicsMapping : public edm::one::EDAnalyzer<> { edm::ESGetToken dspecToken_; }; - TestBTLElectronicsMapping::TestBTLElectronicsMapping(const edm::ParameterSet& iConfig) - : tag_(iConfig.getParameter("DDDetector")), - ddTopNodeName_(iConfig.getUntrackedParameter("ddTopNodeName", "BarrelTimingLayer")), - thisN_(), - btlNS_(){ + : tag_(iConfig.getParameter("DDDetector")), + ddTopNodeName_(iConfig.getUntrackedParameter("ddTopNodeName", "BarrelTimingLayer")), + thisN_(), + btlNS_() { mtdtopoToken_ = esConsumes(); dddetToken_ = esConsumes(tag_); dspecToken_ = esConsumes(tag_); } void TestBTLElectronicsMapping::analyze(const edm::Event& iEvent, const edm::EventSetup& iSetup) { - auto pDD = iSetup.getTransientHandle(dddetToken_); auto pSP = iSetup.getTransientHandle(dspecToken_); @@ -89,7 +87,7 @@ void TestBTLElectronicsMapping::analyze(const edm::Event& iEvent, const edm::Eve edm::LogWarning("TestBTLElectronicsMapping") << ddTopNodeName_ << "Not valid top BarrelTimingLayer volume"; return; } - + DDFilteredView fv(pDD.product(), pDD.product()->description()->worldVolume()); fv.next(0); edm::LogInfo("TestBTLElectronicsMapping") << fv.name(); @@ -99,69 +97,74 @@ void TestBTLElectronicsMapping::analyze(const edm::Event& iEvent, const edm::Eve bool insideBTL = false; uint32_t startLevel = 0; - - do { - if (dd4hep::dd::noNamespace(fv.name()) == "BarrelTimingLayer") { + do { + if (dd4hep::dd::noNamespace(fv.name()) == "BarrelTimingLayer") { insideBTL = true; startLevel = fv.navPos().size(); edm::LogInfo("TestBTLElectronicsMapping") << "insideBTL = " << insideBTL; if (static_cast(btlCrysLayout) < static_cast(BTLDetId::CrysLayout::v4)) { edm::LogInfo("DD4hep_TestMTDIdealGeometry") - << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) - << ", use layout 7 (v4) or later!" << std::endl; + << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) + << ", use layout 7 (v4) or later!" << std::endl; } continue; } - + if (insideBTL && fv.navPos().size() < startLevel) { - break; // exited BTL --> break loop + break; // exited BTL --> break loop } - if (!insideBTL) continue; + if (!insideBTL) + continue; std::stringstream ss; theBaseNumber(fv); - + bool isSens = false; - + for (auto const& t : specs) { for (auto const& it : t.second->paths) { - if (dd4hep::dd::compareEqual(dd4hep::dd::noNamespace(fv.name()), dd4hep::dd::realTopName(it))) { - isSens = true; - break; - } + if (dd4hep::dd::compareEqual(dd4hep::dd::noNamespace(fv.name()), dd4hep::dd::realTopName(it))) { + isSens = true; + break; + } } - } - + } + if (isSens) { - std::stringstream sunitt; std::stringstream snum; - + BTLDetId theId(btlNS_.getUnitID(thisN_)); sunitt << theId.rawId(); snum << theId; - + if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { - BTLElectronicsMapping btlElMap = BTLElectronicsMapping(btlCrysLayout); - snum << "\n"; - snum << "----------------------------------------------------------------------------" << std::endl; - snum << " CCBoard: " << btlElMap.CCBoard(theId) << " FEBoard: " << btlElMap.FEBoard(theId) - << " TOFHIRASIC: " << btlElMap.TOFHIRASIC(theId) << "\n SiPMCh minus: " << btlElMap.SiPMCh(theId, 0) - << " plus: " << btlElMap.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlElMap.TOFHIRCh(theId, 0) - << " plus: " << btlElMap.TOFHIRCh(theId, 1) << "\n"; - snum << "\n"; - snum << " DM, SM, chipId : " << theId.dmodule() << ", " << theId.smodule() << ", " << btlElMap.TOFHIRASIC(theId) << " e-link: " << btlElMap.elink(theId) << "\n" - << " DM, SM from e-link: " << btlElMap.elinkToSM(btlElMap.elink(theId)).first << ", " << btlElMap.elinkToSM(btlElMap.elink(theId)).second << "\n"; - snum << "\n"; - snum << " Tray: " << theId.mtdRR() << " RU: " << theId.runit()<< " hs-link : " << btlElMap.hslink(theId) << "\n" - << " RU from hs-link: " << btlElMap.hslinkToRU( btlElMap.hslink(theId) ) << "\n"; - snum << "\n"; - snum << " Tray, side : " << theId.mtdRR() << ", " << theId.mtdSide() << " S-link : " << btlElMap.Slink(theId) << "\n" - << " Tray, side from S-link, HS-link: " << btlElMap.getTrayFromLinks(btlElMap.Slink(theId),btlElMap.hslink(theId)).first << ", " << btlElMap.getTrayFromLinks(btlElMap.Slink(theId),btlElMap.hslink(theId)).second << "\n"; - snum << "----------------------------------------------------------------------------" << std::endl; + BTLElectronicsMapping btlElMap = BTLElectronicsMapping(btlCrysLayout); + snum << "\n"; + snum << "----------------------------------------------------------------------------" << std::endl; + snum << " CCBoard: " << btlElMap.CCBoard(theId) << " FEBoard: " << btlElMap.FEBoard(theId) + << " TOFHIRASIC: " << btlElMap.TOFHIRASIC(theId) << "\n SiPMCh minus: " << btlElMap.SiPMCh(theId, 0) + << " plus: " << btlElMap.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlElMap.TOFHIRCh(theId, 0) + << " plus: " << btlElMap.TOFHIRCh(theId, 1) << "\n"; + snum << "\n"; + snum << " DM, SM, chipId : " << theId.dmodule() << ", " << theId.smodule() << ", " + << btlElMap.TOFHIRASIC(theId) << " e-link: " << btlElMap.elink(theId) << "\n" + << " DM, SM from e-link: " << btlElMap.elinkToSM(btlElMap.elink(theId)).first << ", " + << btlElMap.elinkToSM(btlElMap.elink(theId)).second << "\n"; + snum << "\n"; + snum << " Tray: " << theId.mtdRR() << " RU: " << theId.runit() << " hs-link : " << btlElMap.hslink(theId) + << "\n" + << " RU from hs-link: " << btlElMap.hslinkToRU(btlElMap.hslink(theId)) << "\n"; + snum << "\n"; + snum << " Tray, side : " << theId.mtdRR() << ", " << theId.mtdSide() + << " S-link : " << btlElMap.Slink(theId) << "\n" + << " Tray, side from S-link, HS-link: " + << btlElMap.getTrayFromLinks(btlElMap.Slink(theId), btlElMap.hslink(theId)).first << ", " + << btlElMap.getTrayFromLinks(btlElMap.Slink(theId), btlElMap.hslink(theId)).second << "\n"; + snum << "----------------------------------------------------------------------------" << std::endl; } edm::LogInfo("TestBTLElectronicsMapping") << snum.str(); } diff --git a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc index 46d14108ea8b3..9fa735b7ae17c 100644 --- a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc +++ b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc @@ -157,8 +157,8 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E edm::LogInfo("DD4hep_TestMTDIdealGeometry") << "isBarrel = " << isBarrel; if (static_cast(btlCrysLayout) < static_cast(BTLDetId::CrysLayout::v4)) { edm::LogInfo("DD4hep_TestMTDIdealGeometry") - << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) - << ", use layout 7 (v4) or later!" << std::endl; + << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) + << ", use layout 7 (v4) or later!" << std::endl; } } else if (dd4hep::dd::noNamespace(fv.name()) == "EndcapTimingLayer") { isBarrel = false; @@ -237,7 +237,7 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E sunitt << theId.rawId(); snum << theId; - if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { + if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { BTLElectronicsMapping btlEM = BTLElectronicsMapping(btlCrysLayout); snum << "\n"; snum << "----------------------------------------------------------------------------" << std::endl; @@ -246,8 +246,8 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E << " plus: " << btlEM.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlEM.TOFHIRCh(theId, 0) << " plus: " << btlEM.TOFHIRCh(theId, 1) << "\n"; snum << "----------------------------------------------------------------------------" << std::endl; - } - } else { + } + } else { ETLDetId theId(etlNS_.getUnitID(thisN_)); sunitt << theId.rawId(); snum << theId; From a270fdd52c64763e0e82e3134f571686968265d4 Mon Sep 17 00:00:00 2001 From: Fabio Cossutti Date: Mon, 11 May 2026 18:52:44 +0200 Subject: [PATCH 5/9] Add spatial location of channels to BTL electronics test output --- .../test/TestBTLElectronicsMapping.cc | 32 +++++++++++++++++-- .../test/DD4hep_TestMTDIdealGeometry.cc | 11 ------- 2 files changed, 30 insertions(+), 13 deletions(-) diff --git a/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc b/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc index b765f1720e398..264680a70e765 100644 --- a/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc +++ b/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc @@ -64,6 +64,10 @@ class TestBTLElectronicsMapping : public edm::one::EDAnalyzer<> { edm::ESGetToken dspecToken_; }; +using DD3Vector = ROOT::Math::DisplacementVector3D>; +using angle_units::operators::convertRadToDeg; +using cms_rounding::roundIfNear0; + TestBTLElectronicsMapping::TestBTLElectronicsMapping(const edm::ParameterSet& iConfig) : tag_(iConfig.getParameter("DDDetector")), ddTopNodeName_(iConfig.getUntrackedParameter("ddTopNodeName", "BarrelTimingLayer")), @@ -141,14 +145,38 @@ void TestBTLElectronicsMapping::analyze(const edm::Event& iEvent, const edm::Eve sunitt << theId.rawId(); snum << theId; + // Compute the crystal ends positions + dd4hep::Box mySens(fv.solid()); + DD3Vector x, y, z; + fv.rotation().GetComponents(x, y, z); + DD3Vector zeroLocal(0., 0., 0.); + DD3Vector plusLocal(mySens.x(), 0., 0.); + DD3Vector plusGlobal = (fv.rotation())(plusLocal) + fv.translation(); + DD3Vector minusLocal(-mySens.x(), 0., 0.); + DD3Vector minusGlobal = (fv.rotation())(minusLocal) + fv.translation(); + if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { + auto fround = [&](double in) { + std::stringstream ss; + ss << std::fixed << std::setw(14) << roundIfNear0(in); + return ss.str(); + }; + + snum << "\n"; + snum << "- location = " << fround(minusGlobal.X() / dd4hep::mm) << fround(minusGlobal.Y() / dd4hep::mm) + << fround(minusGlobal.Z() / dd4hep::mm) << " r = " << fround(minusGlobal.Rho() / dd4hep::mm) + << " phi = " << fround(convertRadToDeg(minusGlobal.Phi())) << "\n"; + snum << "+ location = " << fround(plusGlobal.X() / dd4hep::mm) << fround(plusGlobal.Y() / dd4hep::mm) + << fround(plusGlobal.Z() / dd4hep::mm) << " r = " << fround(plusGlobal.Rho() / dd4hep::mm) + << " phi = " << fround(convertRadToDeg(plusGlobal.Phi())) << "\n"; + BTLElectronicsMapping btlElMap = BTLElectronicsMapping(btlCrysLayout); snum << "\n"; snum << "----------------------------------------------------------------------------" << std::endl; snum << " CCBoard: " << btlElMap.CCBoard(theId) << " FEBoard: " << btlElMap.FEBoard(theId) << " TOFHIRASIC: " << btlElMap.TOFHIRASIC(theId) << "\n SiPMCh minus: " << btlElMap.SiPMCh(theId, 0) - << " plus: " << btlElMap.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlElMap.TOFHIRCh(theId, 0) - << " plus: " << btlElMap.TOFHIRCh(theId, 1) << "\n"; + << " minus: " << btlElMap.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlElMap.TOFHIRCh(theId, 0) + << " minus: " << btlElMap.TOFHIRCh(theId, 1) << "\n"; snum << "\n"; snum << " DM, SM, chipId : " << theId.dmodule() << ", " << theId.smodule() << ", " << btlElMap.TOFHIRASIC(theId) << " e-link: " << btlElMap.elink(theId) << "\n" diff --git a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc index 9fa735b7ae17c..fad2c44bd4fe7 100644 --- a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc +++ b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc @@ -236,17 +236,6 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E BTLDetId theId(btlNS_.getUnitID(thisN_)); sunitt << theId.rawId(); snum << theId; - - if (static_cast(btlCrysLayout) >= static_cast(BTLDetId::CrysLayout::v4)) { - BTLElectronicsMapping btlEM = BTLElectronicsMapping(btlCrysLayout); - snum << "\n"; - snum << "----------------------------------------------------------------------------" << std::endl; - snum << " CCBoard: " << btlEM.CCBoard(theId) << " FEBoard: " << btlEM.FEBoard(theId) - << " TOFHIRASIC: " << btlEM.TOFHIRASIC(theId) << "\n SiPMCh minus: " << btlEM.SiPMCh(theId, 0) - << " plus: " << btlEM.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlEM.TOFHIRCh(theId, 0) - << " plus: " << btlEM.TOFHIRCh(theId, 1) << "\n"; - snum << "----------------------------------------------------------------------------" << std::endl; - } } else { ETLDetId theId(etlNS_.getUnitID(thisN_)); sunitt << theId.rawId(); From aec36baa4620cc2a5ce77608f4e952c55cdf2cef Mon Sep 17 00:00:00 2001 From: Martina Date: Tue, 12 May 2026 12:17:59 +0200 Subject: [PATCH 6/9] fix Tests --- .../MTDObjects/test/TestBTLElectronicsMapping.cc | 5 ++--- Geometry/MTDCommonData/test/BuildFile.xml | 1 - .../test/DD4hep_TestMTDIdealGeometry.cc | 13 ++----------- 3 files changed, 4 insertions(+), 15 deletions(-) diff --git a/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc b/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc index 264680a70e765..e18f78ae4859b 100644 --- a/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc +++ b/CondFormats/MTDObjects/test/TestBTLElectronicsMapping.cc @@ -25,7 +25,6 @@ #include "Geometry/MTDCommonData/interface/MTDBaseNumber.h" #include "Geometry/MTDCommonData/interface/BTLNumberingScheme.h" -//#include "Geometry/MTDCommonData/interface/BTLElectronicsMapping.h" #include "Geometry/MTDCommonData/interface/MTDTopologyMode.h" #include "Geometry/MTDGeometryBuilder/interface/MTDTopology.h" @@ -175,8 +174,8 @@ void TestBTLElectronicsMapping::analyze(const edm::Event& iEvent, const edm::Eve snum << "----------------------------------------------------------------------------" << std::endl; snum << " CCBoard: " << btlElMap.CCBoard(theId) << " FEBoard: " << btlElMap.FEBoard(theId) << " TOFHIRASIC: " << btlElMap.TOFHIRASIC(theId) << "\n SiPMCh minus: " << btlElMap.SiPMCh(theId, 0) - << " minus: " << btlElMap.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlElMap.TOFHIRCh(theId, 0) - << " minus: " << btlElMap.TOFHIRCh(theId, 1) << "\n"; + << " plus: " << btlElMap.SiPMCh(theId, 1) << "\n TOFHIRCh minus: " << btlElMap.TOFHIRCh(theId, 0) + << " plus: " << btlElMap.TOFHIRCh(theId, 1) << "\n"; snum << "\n"; snum << " DM, SM, chipId : " << theId.dmodule() << ", " << theId.smodule() << ", " << btlElMap.TOFHIRASIC(theId) << " e-link: " << btlElMap.elink(theId) << "\n" diff --git a/Geometry/MTDCommonData/test/BuildFile.xml b/Geometry/MTDCommonData/test/BuildFile.xml index d0b6df1c9244c..25ec6655161e5 100644 --- a/Geometry/MTDCommonData/test/BuildFile.xml +++ b/Geometry/MTDCommonData/test/BuildFile.xml @@ -20,7 +20,6 @@ - diff --git a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc index fad2c44bd4fe7..96061fae29816 100644 --- a/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc +++ b/Geometry/MTDCommonData/test/DD4hep_TestMTDIdealGeometry.cc @@ -26,7 +26,6 @@ #include "Geometry/MTDCommonData/interface/MTDBaseNumber.h" #include "Geometry/MTDCommonData/interface/BTLNumberingScheme.h" #include "Geometry/MTDCommonData/interface/ETLNumberingScheme.h" -//#include "Geometry/MTDCommonData/interface/BTLElectronicsMapping.h" #include "Geometry/MTDCommonData/interface/MTDTopologyMode.h" #include "Geometry/MTDGeometryBuilder/interface/MTDTopology.h" @@ -35,8 +34,6 @@ #include "DataFormats/ForwardDetId/interface/BTLDetId.h" #include "DataFormats/ForwardDetId/interface/ETLDetId.h" -#include "CondFormats/MTDObjects/interface/BTLElectronicsMapping.h" - #include "DataFormats/Math/interface/angle_units.h" #include "DataFormats/Math/interface/Rounding.h" #include @@ -87,9 +84,8 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E auto pSP = iSetup.getTransientHandle(dspecToken_); - auto topologyHandle = iSetup.getTransientHandle(mtdtopoToken_); - const MTDTopology* topology = topologyHandle.product(); - auto btlCrysLayout = MTDTopologyMode::crysLayoutFromTopoMode(topology->getMTDTopologyMode()); + //auto topologyHandle = iSetup.getTransientHandle(mtdtopoToken_); + //const MTDTopology* topology = topologyHandle.product(); if (ddTopNodeName_ != "BarrelTimingLayer" && ddTopNodeName_ != "EndcapTimingLayer") { edm::LogWarning("DD4hep_TestMTDIdealGeometry") << ddTopNodeName_ << "Not valid top MTD volume"; @@ -155,11 +151,6 @@ void DD4hep_TestMTDIdealGeometry::analyze(const edm::Event& iEvent, const edm::E if (dd4hep::dd::noNamespace(fv.name()) == "BarrelTimingLayer") { isBarrel = true; edm::LogInfo("DD4hep_TestMTDIdealGeometry") << "isBarrel = " << isBarrel; - if (static_cast(btlCrysLayout) < static_cast(BTLDetId::CrysLayout::v4)) { - edm::LogInfo("DD4hep_TestMTDIdealGeometry") - << "BTL electronics mapping not available for BTL crystal layout " << static_cast(btlCrysLayout) - << ", use layout 7 (v4) or later!" << std::endl; - } } else if (dd4hep::dd::noNamespace(fv.name()) == "EndcapTimingLayer") { isBarrel = false; edm::LogInfo("DD4hep_TestMTDIdealGeometry") << "isBarrel = " << isBarrel; From 6de73749f148be75ec5c17b5bf25c54ebc2ec280 Mon Sep 17 00:00:00 2001 From: Martina Date: Tue, 12 May 2026 12:19:45 +0200 Subject: [PATCH 7/9] minor update --- CondFormats/MTDObjects/interface/BTLElectronicsMapping.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h index f7cde23324582..956659d3af343 100644 --- a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h +++ b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h @@ -234,7 +234,7 @@ class BTLElectronicsMapping { static constexpr uint32_t kNumHSLinks = 72; // number of HS links: in each Serenity 6 trays x 12 links static constexpr uint32_t kOffsetHSLinks = 4; // offset (HS link Ids start from 4 (0-3 reserved) - static constexpr uint32_t MIN_SLINK_ID = 1000; // arbitrary for now + static constexpr uint32_t MIN_SLINK_ID = 0; // arbitrary for now // Define an array of 12 elements, each element is the optical Tx channel Id (this depends on the FF). Then each channel will map to a CC/RU static constexpr std::array optTxCh_n5 = { From cb51d530eee3923a100f0b6fbcea5a8560b23c4c Mon Sep 17 00:00:00 2001 From: Martina Date: Tue, 12 May 2026 12:21:55 +0200 Subject: [PATCH 8/9] code format --- CondFormats/MTDObjects/interface/BTLElectronicsMapping.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h index 956659d3af343..d1e226eee5455 100644 --- a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h +++ b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h @@ -232,9 +232,9 @@ class BTLElectronicsMapping { */ - static constexpr uint32_t kNumHSLinks = 72; // number of HS links: in each Serenity 6 trays x 12 links - static constexpr uint32_t kOffsetHSLinks = 4; // offset (HS link Ids start from 4 (0-3 reserved) - static constexpr uint32_t MIN_SLINK_ID = 0; // arbitrary for now + static constexpr uint32_t kNumHSLinks = 72; // number of HS links: in each Serenity 6 trays x 12 links + static constexpr uint32_t kOffsetHSLinks = 4; // offset (HS link Ids start from 4 (0-3 reserved) + static constexpr uint32_t MIN_SLINK_ID = 0; // arbitrary for now // Define an array of 12 elements, each element is the optical Tx channel Id (this depends on the FF). Then each channel will map to a CC/RU static constexpr std::array optTxCh_n5 = { From aebdbabec571863c8d143b8693d70ab5b2f28351 Mon Sep 17 00:00:00 2001 From: Martina Date: Wed, 13 May 2026 14:00:33 +0200 Subject: [PATCH 9/9] small update --- CondFormats/MTDObjects/interface/BTLElectronicsMapping.h | 4 ++-- CondFormats/MTDObjects/src/BTLElectronicsMapping.cc | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h index d1e226eee5455..24cb754bef37f 100644 --- a/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h +++ b/CondFormats/MTDObjects/interface/BTLElectronicsMapping.h @@ -1,5 +1,5 @@ -#ifndef DATAFORMATS_BTLELECTRONICSMAPPING_H -#define DATAFORMATS_BTLELECTRONICSMAPPING_H 1 +#ifndef CONDFORMATS_MTDOBJECTS_BTLELECTRONICSMAPPING_H +#define CONDFORMATS_MTDOBJECTS_BTLELECTRONICSMAPPING_H 1 #include #include diff --git a/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc b/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc index c081b5844e7af..86b0080807699 100644 --- a/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc +++ b/CondFormats/MTDObjects/src/BTLElectronicsMapping.cc @@ -1,5 +1,4 @@ #include "FWCore/MessageLogger/interface/MessageLogger.h" -//#include "Geometry/MTDCommonData/interface/BTLElectronicsMapping.h" #include "CondFormats/MTDObjects/interface/BTLElectronicsMapping.h" #include "FWCore/Utilities/interface/Exception.h" #include