Implementation principle of HFSS/SIwave-style sheet-free circuit ports

[WEIXUEP]

Hi Palace developers,

Are you familiar with the implementation principle of the Circuit Port used in Ansys HFSS driven-terminal designs or in Ansys SIwave?

Such a port is specified by a positive conductor terminal and a reference conductor terminal. In PCB and package models, the terminals may lie on different conductors or layers, where connecting them using an explicit lumped-port sheet may be difficult or inappropriate.

I am exploring the following generalized terminal-port formulation.

1. Identify the terminal conductors

   Identify the PEC connected components containing the positive and reference terminal patches.

2. Define an auxiliary dielectric region

   Select a dielectric region $\Omega_p$ connecting the two terminals. This region is used only to construct an auxiliary terminal distribution and does not represent an additional physical material or conductor.

3. Solve an auxiliary H1 problem

   Solve a weighted Laplace problem on $\Omega_p$:

$$ \nabla\cdot\left(\kappa\nabla\psi\right)=0, $$

with

$$ \psi=1 \quad\text{on the positive terminal}, $$

$$ \psi=0 \quad\text{on the reference terminal}. $$

The lateral boundary of $\Omega_p$ is treated as insulating. The weight $\kappa$ may initially be set to unity.

A floating PEC component intersecting the auxiliary region is treated as an unknown equipotential surface,

$$ \psi=\alpha_k, $$

together with the zero-net-flux condition

$$ \int_{\Gamma_{f,k}} \kappa\nabla\psi\cdot n,dS=0. $$

4. Construct a normalized terminal current functional

   Let $G$ denote the discrete gradient from the H1 space to the Nédélec space, and define

$$ g=-G\psi. $$

Let $M_\kappa$ be the weighted Nédélec L2 mass matrix over the auxiliary region. Define

$$ q=g^T M_\kappa g, $$

and

$$ c=\frac{M_\kappa g}{q}. $$

This gives

$$ c^Tg=1. $$

Because $g$ is obtained from the discrete Laplace problem, $c$ is discretely divergence-free at unconstrained interior H1 degrees of freedom. It can therefore be interpreted as the weak load vector associated with a unit terminal current flowing from the positive terminal to the reference terminal.

The terminal voltage is defined by

$$ V=c^TE. $$

The same vector $c$ is used to inject terminal current into the Maxwell system. Consequently,

$$ E^T(cI)=VI, $$

giving a power-consistent voltage-current pair.

5. Couple the terminal to the driven Maxwell problem

   Let $s=i\omega$, and let $A(\omega)$ denote the driven Maxwell operator.

   For a parallel RLC termination,

$$ Y(\omega)=\frac{1}{R}+\frac{1}{i\omega L}+i\omega C. $$

If $I_s$ is a Norton-equivalent terminal source, the coupled field equation can be written as

$$ \left[A(\omega)+sY(\omega)cc^T\right]E=f+sI_sc. $$

After solving,

$$ V=c^TE, $$

$$ I_{\mathrm{EM}}=I_s-Y(\omega)V, $$

where $I_{\mathrm{EM}}$ is the current entering the electromagnetic domain. The terminal voltage and current can then be converted into incident and reflected power waves for S-parameter extraction.

This construction can also be expressed as a mixed field-circuit system with an explicit terminal-voltage unknown. The low-rank form avoids using $g$ as an explicit global lifting coordinate in the driven field decomposition; only its dual vector $c$ enters the frequency domain Maxwell system.

Do you know whether this is conceptually similar to the internal HFSS or SIwave Circuit Port formulation?

In particular, do these tools construct a distributed conservative current or voltage template between the selected terminals, or do they instead use a virtual integration path, a prescribed filament current, or another matrix-level field-circuit coupling?

I understand that the exact Ansys implementation may not be public. I am mainly interested in whether this harmonic auxiliary problem and power-dual terminal functional are a reasonable approach for adding a sheet-free circuit port to Palace.

References:

• Assigning Circuit Ports in Ansys HFSS
• Creating a port between terminal groups in Ansys SIwave