[BUG] spi_engine_execution.v - Parameter and Port share the same name

[bwabbersen]

Describe the bug
The spi_engine_execution module contains a parameter named ECHO_SCLK and an input port named echo_sclk. This is allowable in pure verilog, but seems to cause issues when instantiating the module within VHDL (using component instantiation).

Vivado returns this error during synthesis:
ERROR: [Synth 8-8892] 'echo_sclk' is already declared in this region

To Reproduce
Steps to reproduce the behavior:

Use the following component declaration in a vhdl file:

component spi_engine_execution is
generic (
    NUM_OF_CS               : integer := 1;
    DEFAULT_SPI_CFG         : integer := 0;
    DEFAULT_CLK_DIV         : integer := 0;
    DATA_WIDTH              : integer := 8;
    NUM_OF_SDI              : integer := 1;
    SDO_DEFAULT             : std_logic_vector(0 downto 0) := "0";
    ECHO_SCLK               : integer := 0;
    SDI_DELAY               : std_logic_vector(1 downto 0) := "00"
);
port (
    clk                     : in  std_logic;
    resetn                  : in  std_logic;
    active                  : out std_logic;
    cmd_ready               : out std_logic;
    cmd_valid               : in  std_logic;
    cmd                     : in  std_logic_vector(15 downto 0);
    sdo_data_valid          : in  std_logic;
    sdo_data_ready          : out std_logic;
    sdo_data                : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    sdi_data_ready          : in  std_logic;
    sdi_data_valid          : out std_logic;
    sdi_data                : out std_logic_vector(NUM_OF_SDI * DATA_WIDTH-1 downto 0);
    sync_ready              : in  std_logic;
    sync_valid              : out std_logic;
    sync                    : out std_logic_vector(7 downto 0);
    echo_sclk               : in  std_logic;
    sclk                    : out std_logic;
    sdo                     : out std_logic;
    sdo_t                   : out std_logic;
    sdi                     : in  std_logic_vector(NUM_OF_SDI-1 downto 0);
    cs                      : out std_logic_vector(NUM_OF_CS-1 downto 0);
    three_wire              : out std_logic
);

Run synthesis using vivado

Expected behavior
To support multi-language projects, the parameter names should be different from the port names.

Desktop

• Project name and used carrier board: ZC706
• Used Software: Ubuntu/Petalinux
• Tool version: Vivado 2022.2
• HDL Release version: hdl_2021_r1 (though the issue still appears to exist in the latest git release of this file)