In the cic_int module (library/util_cic/cic_int.v), the state register's initial value depends entirely on its declaration assignment: reg [DATA_WIDTH-1:0] state = 'h00.
While this may work in FPGA implementations, it is non-portable (relies on vendor-specific initialization behavior) and non-resettable (lacks a proper reset mechanism)
Is this an intentional design choice or an oversight? If the latter, I recommend adding a reset to ensure predictable initialization and improve library reusability.
In the
cic_intmodule (library/util_cic/cic_int.v), thestateregister's initial value depends entirely on its declaration assignment:reg [DATA_WIDTH-1:0] state = 'h00.While this may work in FPGA implementations, it is non-portable (relies on vendor-specific initialization behavior) and non-resettable (lacks a proper reset mechanism)
Is this an intentional design choice or an oversight? If the latter, I recommend adding a reset to ensure predictable initialization and improve library reusability.