Update Project

* Bump sub-projects
* Update Container to elements:v2.0
* Split ElemRV in two different SoCs
* Migrate from AMBA to BMB + Wishbone
* Move firmware code to software/
* Add SPDX header
* Update firmware core

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>

Author: dnltz

.gitignore

@@ -1,3 +1,8 @@
+# SPDX-FileCopyrightText: 2025 aesc silicon
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
+
 build/
 modules/
 oss-cad-suite/

README.rst

@@ -1,3 +1,7 @@
+.. SPDX-FileCopyrightText: 2025 aesc silicon
+..
+.. SPDX-License-Identifier: CERN-OHL-W-2.0
+
 ElemRV - End-to-end Open-Source RISC-V MCU
 ==========================================
 
@@ -140,6 +144,7 @@ Known Issues
 License
 #######
 
-Copyright (c) 2024 Steffen Reith and Daniel Schultz. Released under the `GPLv3 license`_.
+Copyright (c) 2025 aesc silicon. Released under the `CERN-OHL-W-2.0`_ and `Apache-2.0`_ license.
 
-.. _GPLv3 license: COPYING.GPLv3
+.. _CERN-OHL-W-2.0: LICENSES/CERN-OHL-W-2.0.txt
+.. _Apache-2.0: LICENSES/Apache-2.0.txt

Taskfile.yml

@@ -1,3 +1,7 @@
+# SPDX-FileCopyrightText: 2025 aesc silicon
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 version: '3'
 
 includes:
@@ -7,9 +11,6 @@ includes:
     flatten: true
 
 env:
-  package: "elemrv"
-  SOC: ElemRV
-  CONTAINER_NAME: elemrv_container
   FPGA_FAMILY: ecp5
   FPGA_DEVICE: um5g-45k
   FPGA_PACKAGE: CABGA554
@@ -23,6 +24,12 @@ env:
   BUILD_ROOT: "{{ .PWD }}/build/"
   GCC: "/opt/elements/zephyr-sdk-0.17.0/riscv64-zephyr-elf/bin/riscv64-zephyr-elf"
   OPENROAD_FLOW_ROOT: "{{ .PWD }}/tools/OpenROAD-flow-scripts/flow"
+
+vars:
+  SOC: '{{.SOC | default "ElemRV-N"}}'
+  package:
+    sh: echo "{{.SOC}}" | tr '[:upper:]' '[:lower:]' | tr '-' '_'
+  CONTAINER_NAME: elemrv_container
   CONTAINER_ENV: " \
     -e SOC={{ .SOC }} \
     -e FPGA_FAMILY={{ .FPGA_FAMILY }} \
@@ -47,7 +54,7 @@ tasks:
       - venv/bin/pip3 install podman-compose==1.0.6
       - curl https://storage.googleapis.com/git-repo-downloads/repo > repo
       - chmod a+rx repo
-      - ./repo init -u https://github.com/aesc-silicon/ElemRV.git -b {{if .branch}}{{.branch}}{{else}}main{{end}} -m manifest.xml
+      - ./repo init -u https://github.com/aesc-silicon/ElemRV.git -b {{if .branch}}{{.branch}}{{else}}main{{end}} -m manifest{{if .nightly}}-nightly{{end}}.xml
 
   build-container:
     desc: Creates a container with all necessary host requirements pre-installed.
@@ -65,14 +72,14 @@ tasks:
       - task: repo-sync
     vars:
       branch: "main"
+      nightly: "false"
 
   fpga-prepare:
     desc: Produces the Verilog file and metadata needed for FPGA operations.
     cmds:
       - task: lib-generate
         vars:
           board: "ECPIX5"
-          package: "elemrv"
   fpga-synthesize:
     desc: Generates the FPGA bitstream by synthesizing the design.
     cmds:
@@ -86,19 +93,29 @@ tasks:
       - task: lib-flash-bitstream
         vars:
           board: "ECPIX5"
+  fpga-simulate:
+    desc: Runs simulations at the RTL level. Add 'duration=n' to specify the duration in n milliseconds.
+    cmds:
+      - task: lib-simulate
+        vars:
+          board: "ECPIX5"
+  fpga-view-simulation:
+    desc: Opens the simulation with GTKWave.
+    cmds:
+      - task: lib-view-simulation
+        vars:
+          board: "ECPIX5"
 
   compile-firmware:
      desc: Compiles bare metal firmwares.
      cmds:
        - task: lib-baremetal-firmware
          vars:
           board: "SG13G2"
-          package: "elemrv"
           app: "bootrom"
        - task: lib-baremetal-firmware
          vars:
           board: "SG13G2"
-          package: "elemrv"
           app: "demo"
 
   prepare:
@@ -107,27 +124,23 @@ tasks:
       - task: lib-generate
         vars:
           board: "SG13G2"
-          package: "elemrv"
       - task: lib-sealring
         vars:
           board: "SG13G2"
-      - cp {{ .NAFARR_BASE }}/hardware/scala/nafarr/crypto/aes/AESMasked.v {{ .BUILD_ROOT }}/ElemRV/SG13G2/zibal/
 
   simulate:
     desc: Runs simulations at the RTL level. Add 'duration=n' to specify the duration in n milliseconds.
     cmds:
       - task: lib-simulate
         vars:
           board: "SG13G2"
-          package: "elemrv"
 
   view-simulation:
     desc: Opens the simulation with GTKWave.
     cmds:
       - task: lib-view-simulation
         vars:
           board: "SG13G2"
-          package: "elemrv"
 
   layout:
     desc: Creates the physical layout of the chip.

build.sbt

@@ -1,3 +1,7 @@
+// SPDX-FileCopyrightText: 2025 aesc silicon
+//
+// SPDX-License-Identifier: CERN-OHL-W-2.0
+
 val spinalVersion = "1.10.2a"
 
 lazy val root = (project in file("."))