ElemRV/.travis.yml at main · aesc-silicon/ElemRV · GitHub

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# SPDX-FileCopyrightText: 2025 aesc silicon
#
# SPDX-License-Identifier: CERN-OHL-W-2.0

language: generic

os: linux
dist: noble

# Only run on pull requests to main branch
branches:
  only:
    - main

# Set timeout to 180 minutes
timeout: 10800

# Conditional logic for PRs vs Cron
if: type IN (pull_request, cron)

cache:
  directories:
    - $HOME/.podman-cache

install:
  # Install Podman
  - sudo apt-get update
  - sudo apt-get install -y podman uidmap slirp4netns

  # Disable color
  - git config --global color.ui false

  # Install other dependencies
  - sudo snap install task --classic
  - sudo apt-get update
  - sudo apt-get install -y virtualenv

script:
  # Use appropriate branch: PR branch for PRs, main for cron
  - |
    if [ "$TRAVIS_EVENT_TYPE" = "cron" ]; then
      BRANCH="main"
      MANIFEST_SUFFIX="manifest_suffix=-nightly"
    else
      BRANCH="${TRAVIS_PULL_REQUEST_BRANCH:-main}"
      MANIFEST_SUFFIX=""
    fi

  # Prepare the project
  - CI=true IS_HEADLESS=true task install branch=${BRANCH} ${MANIFEST_SUFFIX}
  - CI=true IS_HEADLESS=true task install-zephyr

  # Prepare files
  - CI=true IS_HEADLESS=true task SOC=ElemRV-H TARGET=SG13CMOS5L asic:prepare
  - CI=true IS_HEADLESS=true task SOC=ElemRV-C TARGET=SG13CMOS5L asic:prepare
  - CI=true IS_HEADLESS=true task SOC=ElemRV-N TARGET=SG13CMOS5L asic:prepare

  # Compile baremetal firmware
  - CI=true IS_HEADLESS=true task SOC=ElemRV-H baremetal:compile
  - CI=true IS_HEADLESS=true task SOC=ElemRV-C baremetal:compile
  - CI=true IS_HEADLESS=true task SOC=ElemRV-N baremetal:compile

  # Prepare FPGA files
  - CI=true IS_HEADLESS=true task SOC=ElemRV-H TARGET=SG13CMOS5L fpga:prepare
  - CI=true IS_HEADLESS=true task SOC=ElemRV-C TARGET=SG13CMOS5L fpga:prepare
  - CI=true IS_HEADLESS=true task SOC=ElemRV-N TARGET=SG13CMOS5L fpga:prepare

  # TODO ElemRV-C is currently missing in Zephyr
  # Compile Zephyr firmware
  - CI=true IS_HEADLESS=true task SOC=ElemRV-H zephyr:compile
  #- CI=true IS_HEADLESS=true task SOC=ElemRV-C zephyr:compile
  - CI=true IS_HEADLESS=true task SOC=ElemRV-N zephyr:compile

  # Synthesize FPGA design
  - CI=true IS_HEADLESS=true travis_wait 20 task SOC=ElemRV-H TARGET=SG13CMOS5L fpga:synthesize
  - CI=true IS_HEADLESS=true travis_wait 20 task SOC=ElemRV-C TARGET=SG13CMOS5L fpga:synthesize
  - CI=true IS_HEADLESS=true travis_wait 20 task SOC=ElemRV-N TARGET=SG13CMOS5L fpga:synthesize

  # TODO Full RTL to GDS flow takes too long for travis
  # Generate layout
  #- CI=true IS_HEADLESS=true task SOC=ElemRV-H TARGET=SG13CMOS5L asic:build

  # Add metal fill
  #- CI=true IS_HEADLESS=true task SOC=ElemRV-H TARGET=SG13CMOS5L asic:fill

  # Run maximal DRC
  #- CI=true IS_HEADLESS=true task SOC=ElemRV-H TARGET=SG13CMOS5L asic:drc

notifications:
  email:
    on_success: never
    on_failure: always
    recipients:
      - nightly.reports@aesc-silicon.de