tests pass locally

Author: WilliamZhang20

test/Makefile

@@ -60,6 +60,16 @@ test-top:
 		WAVES_DIR=$(WAVES_ROOT)/tpu/wave \
 		COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/tpu/wave/tpu_tb_$(TIMESTAMP).vcd\""'
 
+test-systolic-array:
+	$(MAKE) clean
+	$(MAKE) sim \
+        TOPLEVEL=systolic_array_tb \
+        MODULE=test_systolic_array \
+        VERILOG_SOURCES="$(WAVES_ROOT)/systolic_array/systolic_array_tb.v $(SRC_DIR)/systolic_array_2x2.v $(SRC_DIR)/PE.v" \
+        PYTHONPATH=$(WAVES_ROOT)/systolic_array \
+        WAVES_DIR=$(WAVES_ROOT)/systolic_array/wave \
+        COMPILE_ARGS='$(COMPILE_ARGS) -DVCD_PATH="\"$(WAVES_ROOT)/systolic_array/wave/systolic_array_tb_$(TIMESTAMP).vcd\""'
+
 test-memory:
 	$(MAKE) clean
 	$(MAKE) sim \

test/memory/memory_tb.v

@@ -1,7 +1,7 @@
 `default_nettype none
 `timescale 1ns / 1ps
 
-module memory_tb;
+module memory_tb ();
 
 	// Dump the signals to a VCD file. You can view it with gtkwave or surfer.
 	initial begin
@@ -11,6 +11,7 @@ module memory_tb;
 		$dumpfile("memory_tb.vcd");
 `endif
 		$dumpvars(0, memory_tb);
+		#1;
 	end
 
 	// Inputs
@@ -26,23 +27,19 @@ module memory_tb;
 
 	// Instantiate the memory module
 	memory dut (
-`ifdef GL_TEST
-      .VPWR(VPWR),
-      .VGND(VGND),
-`endif
-			.clk(clk),
-			.rst(rst),
-			.write_en(write_en),
-			.addr(addr),
-			.in_data(in_data),
-			.weight0(weight0),
-			.weight1(weight1),
-			.weight2(weight2),
-			.weight3(weight3),
-			.input0(input0),
-			.input1(input1),
-			.input2(input2),
-			.input3(input3)
+		.clk(clk),
+		.rst(rst),
+		.write_en(write_en),
+		.addr(addr),
+		.in_data(in_data),
+		.weight0(weight0),
+		.weight1(weight1),
+		.weight2(weight2),
+		.weight3(weight3),
+		.input0(input0),
+		.input1(input1),
+		.input2(input2),
+		.input3(input3)
 	);
 
 endmodule

test/systolic_array/__pycache__/test_systolic_array.cpython-312-pytest-8.3.4.pyc

@@ -0,0 +1,48 @@
+`default_nettype none
+`timescale 1ns / 1ps
+
+module systolic_array_tb;
+
+    initial begin
+`ifdef VCD_PATH
+        $dumpfile(`VCD_PATH);
+`else
+		$dumpfile("systolic_array_tb.vcd");
+`endif
+		$dumpvars(0, systolic_array_tb);
+        #1;
+	end
+
+  // Inputs
+  reg clk;
+  reg rst;
+  reg clear;
+  reg activation;
+  reg signed [7:0] a_data0;
+  reg signed [7:0] a_data1;
+  reg signed [7:0] b_data0;
+  reg signed [7:0] b_data1;
+
+  // Outputs
+  wire signed [11:0] c00;
+  wire signed [11:0] c01;
+  wire signed [11:0] c10;
+  wire signed [11:0] c11;
+
+  // Instantiate the systolic array module
+  systolic_array_2x2 #(.WIDTH(8)) dut (
+      .clk(clk),
+      .rst(rst),
+      .clear(clear),
+      .activation(activation),
+      .a_data0(a_data0),
+      .a_data1(a_data1),
+      .b_data0(b_data0),
+      .b_data1(b_data1),
+      .c00(c00),
+      .c01(c01),
+      .c10(c10),
+      .c11(c11)
+  );
+  
+endmodule

test/systolic_array/systolic_array_tb.v

@@ -0,0 +1,85 @@
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer, ClockCycles
+
+@cocotb.test()
+async def test_systolic_array_basic(dut):
+    """Test basic 2x2 matrix multiplication"""
+
+    cocotb.log.info("Starting systolic array test")
+
+    clock = Clock(dut.clk, 10, units="ns")  # 100 MHz
+    cocotb.start_soon(clock.start())
+
+    # Reset
+    dut.rst.value = 1
+    dut.clear.value = 1
+    dut.activation.value = 0
+    dut.a_data0.value = 0
+    dut.a_data1.value = 0
+    dut.b_data0.value = 0
+    dut.b_data1.value = 0
+    await Timer(20, units="ns")
+
+    dut.rst.value = 0
+    dut.clear.value = 1
+    await RisingEdge(dut.clk)
+
+    dut.clear.value = 0
+    await RisingEdge(dut.clk)
+
+    matrix_A = [[1, 2], [3, 4]]
+    matrix_B = [[5, 6], [7, 8]]
+
+    weights = [matrix_A[0][0], matrix_A[0][1], matrix_A[1][0], matrix_A[1][1]]  # weight0..3
+    inputs = [matrix_B[0][0], matrix_B[1][0], matrix_B[0][1], matrix_B[1][1]]   # input0..3
+
+    # Drive cycle 0: mmu_cycle = 3'b000
+    dut.a_data0.value = weights[0]  # weight0
+    dut.a_data1.value = 0
+    dut.b_data0.value = inputs[0]   # input0
+    dut.b_data1.value = 0
+    await RisingEdge(dut.clk)
+
+    # Drive cycle 1: mmu_cycle = 3'b001
+    dut.a_data0.value = weights[1]  # weight1
+    dut.a_data1.value = weights[2]  # weight2
+    dut.b_data1.value = inputs[2]   # input2 (not transposed)
+    dut.b_data0.value = inputs[1]   # input1
+    await RisingEdge(dut.clk)
+
+    # Drive cycle 2: mmu_cycle = 3'b010
+    dut.a_data0.value = 0
+    dut.a_data1.value = weights[3]  # weight3
+    dut.b_data0.value = 0
+    dut.b_data1.value = inputs[3]   # input3
+    await RisingEdge(dut.clk)
+
+    # Clear inputs for subsequent cycles (3'b011..3'b101)
+    dut.a_data0.value = 0
+    dut.a_data1.value = 0
+    dut.b_data0.value = 0
+    dut.b_data1.value = 0
+
+    # Wait for 2 more cycles to let systolic array process
+    await ClockCycles(dut.clk, 2)
+
+    # Read outputs
+    c00 = dut.c00.value.signed_integer
+    c01 = dut.c01.value.signed_integer
+    c10 = dut.c10.value.signed_integer
+    c11 = dut.c11.value.signed_integer
+
+    cocotb.log.info(f"Output matrix C:")
+    cocotb.log.info(f"C00 = {c00}")
+    cocotb.log.info(f"C01 = {c01}")
+    cocotb.log.info(f"C10 = {c10}")
+    cocotb.log.info(f"C11 = {c11}")
+
+    # Check results
+    assert c00 == 19, f"C00 expected 19 but got {c00}"
+    assert c01 == 22, f"C01 expected 22 but got {c01}"
+    assert c10 == 43, f"C10 expected 43 but got {c10}"
+    assert c11 == 50, f"C11 expected 50 but got {c11}"
+
+    cocotb.log.info("Systolic array multiplication test passed")

test/systolic_array/test_systolic_array.py

@@ -22,20 +22,9 @@ module tb ();
   wire [7:0] uo_out;
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
-`ifdef GL_TEST
-  wire VPWR = 1'b1;
-  wire VGND = 1'b0;
-`endif
 
   // Replace tt_um_example with your module name:
   tt_um_tpu tpu_project (
-
-      // Include power ports for the Gate Level test:
-`ifdef GL_TEST
-      .VPWR(VPWR),
-      .VGND(VGND),
-`endif
-
       .ui_in  (ui_in),    // Dedicated inputs
       .uo_out (uo_out),   // Dedicated outputs
       .uio_in (uio_in),   // IOs: Input path