clean up buggy code

Author: WilliamZhang20

src/control_unit.v

@@ -76,6 +76,7 @@ module control_unit (
             mem_addr <= 0;
         end else begin
             state <= next_state;
+            mem_addr <= 0;
             case (state)
                 S_IDLE: begin
                     mat_elems_loaded <= 0;
@@ -92,7 +93,6 @@ module control_unit (
                         mem_addr <= mat_elems_loaded + 1;
                     end else begin
                         mem_load_mat <= 0;
-                        mem_addr <= 0;
                     end
 
                     if (mat_elems_loaded == 3'b111) begin 
@@ -104,7 +104,6 @@ module control_unit (
                 S_MMU_FEED_COMPUTE_WB: begin
                     mmu_en <= 1;
                     mem_load_mat <= 0;
-                    mem_addr <= 0;
 					mmu_cycle <= mmu_cycle + 1;
                 end
 
@@ -113,11 +112,6 @@ module control_unit (
                     mmu_cycle <= 0;
                     mmu_en <= 0;
                     mem_load_mat <= load_en;
-                    if (load_en) begin
-                        mem_addr <= 0;
-                    end else begin
-                        mem_addr <= 0;
-                    end
 				end
             endcase
         end