increase clock cycle to real clock

Author: WilliamZhang20

.gitignore

@@ -7,5 +7,6 @@ src/user_config.json
 src/config_merged.json
 test/sim_build
 test/*/__pycache__/
+test/__pycache__/
 test/results.xml
 test/gate_level_netlist.v

info.yaml

@@ -5,7 +5,7 @@ project:
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "multiplies matrices"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     50       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     1000000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2