Add OpenOFDM 802.11 OFDM decoder

[mguthaus]

Design: OpenOFDM

Repository: https://github.com/jhshi/openofdm (active fork: https://github.com/open-sdr/openofdm)
License: Apache-2.0
Language: Verilog
Stars: 465

Description

A synthesizable, modular Verilog implementation of an 802.11 OFDM PHY decoder. Supports 802.11a/g (all bit rates) and 802.11n (20MHz BW, MCS 0-7). Takes 32-bit I/Q samples as input and outputs decoded packet bytes.

Why it's a good benchmark candidate

• New architecture: First wireless PHY / signal processing pipeline in the suite. A completely new design category — no overlap with existing processors, accelerators, or network MACs.
• Large design: Full receive chain with deep pipeline: synchronization → FFT → channel estimation → equalization → deinterleaving → Viterbi decoding → descrambling. Bundles multiple DSP blocks into a realistic system-level design.
• Industry-relevant: 802.11 WiFi is ubiquitous. OFDM decoders are a staple of wireless ASIC/FPGA design and representative of real signal processing workloads.
• Active development: The open-sdr fork was updated Feb 2026 and is used in the openwifi project (open-source WiFi chip).

Estimated complexity

• Gate count: Large (FFT engine, Viterbi decoder, channel estimator, equalizer, control logic)
• Memories: Yes — FFT buffers, interleaver/deinterleaver storage, Viterbi traceback memory will need FakeRAM
• IO count: Medium (32-bit I/Q input, decoded byte output, control signals)

Verification

Verified on Ettus Research USRP N210 hardware. Includes simulation test inputs (both simulated and captured over-the-air). Documentation at openofdm.readthedocs.io.

Conversion notes

Pure Verilog — no conversion needed. May need to stub out or exclude any USRP-specific I/O wrappers; the core dot11 module is self-contained.

Target platforms

• asap7
• nangate45
• sky130hd

[jingyis-1024]

but it only works for 4 hours ,do you have any solution?

[mguthaus]

Closing — after investigating the source, OpenOFDM isn't a viable ASIC benchmark as-is, on two counts:

1. The repo bundles proprietary Xilinx IP. Of the 1245 .v files in open-sdr/openofdm @ 2f0e0ba9, 1206 are the vendored Xilinx ISE 12.2 CoreLib (verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/). Those are Xilinx-copyrighted and not covered by the repo's Apache-2.0 license, so HighTide can't http_archive/redistribute the repo, and we'd have to carefully exclude that whole tree.

2. The core datapath depends on non-synthesizable Xilinx LogiCORE IP. The 39 OpenOFDM-authored files instantiate Xilinx CoreGen cores — xfft_v7_1 (FFT), viterbi_v7_0 (Viterbi decoder), complex_multiplier, div_gen_v3_0 — which ship only as simulation/netlist models, not synthesizable RTL. Contrary to the issue's "pure Verilog, no conversion" note, adding OpenOFDM would mean replacing the entire DSP datapath (FFT, Viterbi, complex mult, divider) with open synthesizable cores — effectively rebuilding the design.

The wireless-PHY category is still appealing, but this particular implementation isn't a clean fit. A prerequisite would be an open synthesizable FFT such as ZipCPU's dblclockfft (#31); a self-contained open Viterbi decoder would be the other piece. Closing this in favor of cleaner DSP/crypto candidates (e.g. #31 dblclockfft, #29 secworks/aes).