Upstream update available: designs/src/litepci/dev/repo
- Repo: enjoy-digital/litepcie
- Branch: master
- Pinned:
95f47311 (2026-05-11)
- Upstream:
6cb29652 (2026-06-01)
- Behind: 15 commits / 21 days
Severity: MODERATE
Real TLP packetizer fix (continuous 128-bit 4DW payload kept in DATA), plus several driver-side fixes (liteuart polling robustness, DMA mmap of coherent buffers, shared DMA fd in user-space). Test suite reorg + same SoCCore import rename we've seen on liteeth/litedram.
Commits
9d332cd test: split slow tests from default CI37c4b12 test: make simulation VCD dumps opt-in4653b9a test: trim high-level simulation workloads3a13f28 test: isolate example build outputsb08c6b5 test: align test style with LiteX conventionsa3cae57 test: keep generated metadata in temp outputs00e5bcf tlp/packetizer: keep 128-bit 4DW payload in DATAb5c8f01 software/user: support shared DMA device fd43a21eb software: add PCIe rescan utilitye5f4760 software/kernel/liteuart: improve RX/TX polling robustnessc52a6fe software/kernel: fix DMA mmap of coherent buffersc1b2d8c test: cover continuous 128-bit 4DW payload handoffce2dde2 Bump to version 2026.041816639 ci: make PyPI publishing manual6cb2965 integration: use canonical SoCCore imports
What changed
- TLP packetizer fix — 128-bit 4DW payload now kept in DATA across continuous handoff (with new test coverage); RTL-level fix.
- Driver/software — DMA mmap of coherent buffers fixed;
liteuart polling robustness; PCIe rescan utility; shared DMA fd in user-space.
- Test reorg — slow tests split out, VCD opt-in, workloads trimmed, generated metadata kept in temp, example output isolation.
- Integration imports — canonical
SoCCore rename.
- Version bump to 2026.04.
Recommendation
Defer to next refresh sweep. The TLP packetizer fix is the only RTL-relevant change for the HighTide litepci build path. Given this design currently carries the OpenROAD CTS-0122 patch workaround (CLAUDE.md), bumping should coincide with a fresh RTL → GDS validation across all three platforms. Worth pulling on the next scheduled litex/litepcie refresh together with liteeth + litedram (same SoCCore import refactor across all three).
Last refreshed: 2026-06-01T10:41:57Z
Upstream update available:
designs/src/litepci/dev/repo95f47311(2026-05-11)6cb29652(2026-06-01)Severity: MODERATE
Real TLP packetizer fix (continuous 128-bit 4DW payload kept in DATA), plus several driver-side fixes (
liteuartpolling robustness, DMA mmap of coherent buffers, shared DMA fd in user-space). Test suite reorg + sameSoCCoreimport rename we've seen on liteeth/litedram.Commits
9d332cdtest: split slow tests from default CI37c4b12test: make simulation VCD dumps opt-in4653b9atest: trim high-level simulation workloads3a13f28test: isolate example build outputsb08c6b5test: align test style with LiteX conventionsa3cae57test: keep generated metadata in temp outputs00e5bcftlp/packetizer: keep 128-bit 4DW payload in DATAb5c8f01software/user: support shared DMA device fd43a21ebsoftware: add PCIe rescan utilitye5f4760software/kernel/liteuart: improve RX/TX polling robustnessc52a6fesoftware/kernel: fix DMA mmap of coherent buffersc1b2d8ctest: cover continuous 128-bit 4DW payload handoffce2dde2Bump to version 2026.041816639ci: make PyPI publishing manual6cb2965integration: use canonical SoCCore importsWhat changed
liteuartpolling robustness; PCIe rescan utility; shared DMA fd in user-space.SoCCorerename.Recommendation
Defer to next refresh sweep. The TLP packetizer fix is the only RTL-relevant change for the HighTide litepci build path. Given this design currently carries the OpenROAD CTS-0122 patch workaround (CLAUDE.md), bumping should coincide with a fresh RTL → GDS validation across all three platforms. Worth pulling on the next scheduled litex/litepcie refresh together with liteeth + litedram (same
SoCCoreimport refactor across all three).Last refreshed: 2026-06-01T10:41:57Z