webpage: LitePCI asap7 added; rename LitePCIe -> LitePCI; data-leaves on non-derivable portfolio rows

Add the asap7 LitePCI results row, gallery thumb, and a new portfolio entry
on index.html.  Rename the display name LitePCIe -> LitePCI everywhere on
the webpage (gallery card h2, alt text, body paragraph, portfolio row, skill
mapping) to match the design-dir name `litepci/`; upstream URL and the
generic "PCIe" protocol references stay unchanged.

Add data-leaves attribute to the three portfolio <tr>s whose leaf name(s)
are not derivable from the display name by simple case-fold / space-strip:
  <tr data-leaves="bp_uno bp_quad">         BlackParrot (two members)
  <tr data-leaves="liteeth_udp_usp_gth_sgmii">  LiteEth (one variant, name diverges)
  <tr data-leaves="partition_*">            NVDLA (family glob)

This is the index.html side of the update-results skill's data-leaves
convention; the skill's Step 8 is being refactored separately to consume
these attributes instead of carrying its own hardcoded mapping.

nangate45 and sky130hd LitePCI rows preserved at their existing SHAs
(c941d62 / 5777394) with "skipped: not cached on 2026-05-21" comment
markers; their fresh data will land on the next sweep once the in-flight
k8s _gallery builds at litepci-n45-sky-fakeram-recovery (6c8ff0d) cache.

Author: mguthaus

figures/litepci_asap7_01ca8768.png

@@ -526,10 +526,10 @@ <h2><a href="https://github.com/enjoy-digital/liteeth">LiteEth</a></h2>
       </div>
     </div>
 
-    <!-- LitePCIe -->
+    <!-- LitePCI -->
     <div class="design-card">
       <div class="design-header">
-        <h2><a href="https://github.com/enjoy-digital/litepcie">LitePCIe</a></h2>
+        <h2><a href="https://github.com/enjoy-digital/litepcie">LitePCI</a></h2>
         <div class="badges">
           <span class="lang-badge">Python (Migen/LiteX)</span>
           <span class="platform-badge badge-asap7">asap7</span>
@@ -540,14 +540,14 @@ <h2><a href="https://github.com/enjoy-digital/litepcie">LitePCIe</a></h2>
       <div class="design-body">
         <div class="design-image">
           <div class="design-thumbs">
-            <div class="thumb-placeholder"><div class="ph-box">pending</div><span class="thumb-label asap7">asap7</span></div>
-            <a class="thumb-link" href="figures/litepci_nangate45_c941d626.png"><img src="figures/thumbs/litepci_nangate45_c941d626.jpg" alt="LitePCIe nangate45 final"><span class="thumb-label nangate45">nangate45</span></a>
+            <a class="thumb-link" href="figures/litepci_asap7_01ca8768.png"><img src="figures/thumbs/litepci_asap7_01ca8768.jpg" alt="LitePCI asap7 final"><span class="thumb-label asap7">asap7</span></a>
+            <a class="thumb-link" href="figures/litepci_nangate45_c941d626.png"><img src="figures/thumbs/litepci_nangate45_c941d626.jpg" alt="LitePCI nangate45 final"><span class="thumb-label nangate45">nangate45</span></a>
             <div class="thumb-placeholder"><div class="ph-box">pending</div><span class="thumb-label sky130hd">sky130hd</span></div>
           </div>
         </div>
         <div class="design-info">
           <p>
-            LitePCIe is the LiteX project's PCIe endpoint IP — a small-footprint, configurable
+            LitePCI is the LiteX project's PCIe endpoint IP — a small-footprint, configurable
             PCIe Gen2/3 controller generated from Python / Migen. This configuration targets the
             Xilinx UltraScale+ <code>pcie_us</code> hard-IP PHY (committed as a LEF/LIB blackbox
             with a 1000×1000 µm footprint) and five FakeRAM macros for the DMA buffer set.

figures/thumbs/litepci_asap7_01ca8768.jpg

@@ -847,7 +847,7 @@ <h2 class="section-title">Design Portfolio</h2>
             </tr>
           </thead>
           <tbody>
-            <tr>
+            <tr data-leaves="bp_uno bp_quad">
               <td><strong>BlackParrot</strong></td>
               <td>RISC-V multicore processor (unicore &amp; quad core variants)</td>
               <td><span class="lang-badge">SystemVerilog</span></td>
@@ -916,7 +916,7 @@ <h2 class="section-title">Design Portfolio</h2>
                 <span class="platform-badge badge-sky130hd">sky130hd</span>
               </td>
             </tr>
-            <tr>
+            <tr data-leaves="liteeth_udp_usp_gth_sgmii">
               <td><strong>LiteEth</strong></td>
               <td>Lightweight Ethernet core (UDP / Xilinx UltraScale+ GTH SGMII)</td>
               <td><span class="lang-badge">Python (Migen/LiteX)</span></td>
@@ -926,6 +926,14 @@ <h2 class="section-title">Design Portfolio</h2>
                 <span class="platform-badge badge-sky130hd">sky130hd</span>
               </td>
             </tr>
+            <tr>
+              <td><strong>LitePCI</strong></td>
+              <td>Lightweight PCIe endpoint (kcu105 / Xilinx UltraScale+ pcie_us hard-IP)</td>
+              <td><span class="lang-badge">Python (Migen/LiteX)</span></td>
+              <td>
+                <span class="platform-badge badge-asap7">asap7</span>
+              </td>
+            </tr>
             <tr>
               <td><strong>CoralNPU</strong></td>
               <td>Google Coral neural processing unit accelerator</td>
@@ -936,7 +944,7 @@ <h2 class="section-title">Design Portfolio</h2>
                 <span class="platform-badge badge-sky130hd">sky130hd</span>
               </td>
             </tr>
-            <tr>
+            <tr data-leaves="partition_*">
               <td><strong>NVDLA</strong></td>
               <td>NVIDIA Deep Learning Accelerator (5 partitions)</td>
               <td><span class="lang-badge">Verilog</span></td>

gallery.html

@@ -495,6 +495,26 @@ <h1>Build Results</h1>
             <td>6.700</td>
             <td><a href="https://github.com/VLSIDA/HighTide/commit/25d55d07">25d55d07</a></td>
           </tr>
+          <tr data-design="litepci" data-platform="asap7" data-commit="01ca8768">
+            <td><span class="platform-badge badge-asap7">asap7</span></td>
+            <td>litepci</td>
+            <td>652811.0</td>
+            <td>649294.0</td>
+            <td>10896.2</td>
+            <td>75.3</td>
+            <td>74927</td>
+            <td>12762</td>
+            <td>47506</td>
+            <td>14659</td>
+            <td>21</td>
+            <td>875</td>
+            <td>-882.91</td>
+            <td>2231.02</td>
+            <td>0.22</td>
+            <td>55.383</td>
+            <td>2.241</td>
+            <td><a href="https://github.com/VLSIDA/HighTide/commit/01ca8768">01ca8768</a></td>
+          </tr>
           <tr data-design="minimax" data-platform="asap7" data-commit="0db39103">
             <td><span class="platform-badge badge-asap7">asap7</span></td>
             <td>minimax</td>
@@ -855,6 +875,7 @@ <h1>Build Results</h1>
             <td>1.281</td>
             <td><a href="https://github.com/VLSIDA/HighTide/commit/ee2f4d93">ee2f4d93</a></td>
           </tr>
+          <!-- skipped: not cached on 2026-05-21 (k8s build still running at 01ca8768) -->
           <tr data-design="litepci" data-platform="nangate45" data-commit="c941d626">
             <td><span class="platform-badge badge-nangate45">nangate45</span></td>
             <td>litepci</td>
@@ -1175,6 +1196,7 @@ <h1>Build Results</h1>
             <td>13.510</td>
             <td><a href="https://github.com/VLSIDA/HighTide/commit/62cb796e">62cb796e</a></td>
           </tr>
+          <!-- skipped: not cached on 2026-05-21 (k8s build still running at 01ca8768) -->
           <tr data-design="litepci" data-platform="sky130hd" data-commit="5777394e">
             <td><span class="platform-badge badge-sky130hd">sky130hd</span></td>
             <td>litepci</td>